On Sat, Aug 14, 2021 at 11:40:40AM -0700, Colin Foster wrote:
> On Sat, Aug 14, 2021 at 02:47:21PM +0300, Vladimir Oltean wrote:
> > On Fri, Aug 13, 2021 at 07:50:03PM -0700, Colin Foster wrote:
> > > +* phy_mode = "sgmii": on ports 0, 1, 2, 3
> >
> > > + port@0 {
> > > + reg = <0>;
> > > + ethernet = <&mac>;
> > > + phy-mode = "sgmii";
> > > +
> > > + fixed-link {
> > > + speed = <100>;
> > > + full-duplex;
> > > + };
> > > + };
> >
> > Your driver is unconditionally setting up the NPI port at gigabit and
> > you claim it works, yet the device tree sees a 100Mbps fixed-link? Which
> > one is right, what speed does the port operate at?
>
> Good catch!
>
> I made the change to ocelot_spi_vsc7512 yesterday to set it up as
> gigabit, tested it, and it still works. Previously for my testing I'd
> had it hard-coded to 100, because the Beaglebone I'm using only supports
> 100Mbps on eth0.
>
> # phytool print swp1/0
Why are you showing the PHY registers of swp1? Why are these relevant at all?
>
> ieee-phy: id:0x00070540
>
> ieee-phy: reg:BMCR(0x00) val:0x1040
> flags: -reset -loopback [1m+aneg-enable[0m -power-down -isolate -aneg-restart -collision-test
> speed: 1000-half
Also, 1000/half sounds like an odd speed to end negotiation at.
>
> ieee-phy: reg:BMSR(0x01) val:0x796d
> capabilities: -100-b4 [1m+100-f[0m [1m+100-h[0m [1m+10-f[0m [1m+10-h[0m -100-t2-f -100-t2-h
> flags: [1m+ext-status[0m [1m+aneg-complete[0m -remote-fault [1m+aneg-capable[0m [1m+link[0m -jabber [1m+ext-register[0m
>
>
> Of course I understand that "it works" is not the same as "it's correct"
>
> What I wanted to accomplish was to use the speed parameter and set up
> the link based on that. I looked through all the DSA drivers and
> couldn't find anything that seems to do that. The closest thing I saw
> was in mt7531_cpu_port_config where they set the speed to either 2500 or
> 1000 based on the interface. But nothing that I saw would explicitly set
> the speed based on this parameter.
As I mentioned in the other email, .phylink_mac_link_up is the function
you are looking for. Phylink parses the fixed-link and calls that
function for fixed-link ports with the speed and duplex specified. Check
and see if felix_phylink_mac_link_up is not in fact called with
link_an_mode == MLO_AN_FIXED, speed == SPEED_100 and duplex == DUPLEX_FULL,
then what you are doing with that and if it makes sense for what you are
trying to do.
>
> So I think there's something I'm missing. The fixed-link speed should apply to
> the CPU port on the switch (port@0)?
Is this a question? It is under port@0, the port with the 'ethernet'
property i.e. the CPU port, so why should it not?
> Then eth0 can be manually set to a specific speed, but if it doesn't
> match the fixed-link speed I'd be out of luck? Or should an ip link or
> ethtool command to eth0 modify the speeds of both sides of the
> connection? It feels like setting port@0 to the fastest speed and
> letting it negotiate down to eth0 makes sense...
>
> To ask the same question a different way:
>
> I can currently run "ethtool -s eth0 speed 10 duplex full autoneg on"
> and the link at eth0 drops to 10Mbps. Pinging my desktop jumps from
> about 400us to about 600us when I do that.
If eth0 is also a fixed-link, you should not be able to do that, no.
But the fact that you are able to do that means it's not a fixed-link,
you have a pair of PHYs that freely auto-negotiate the speed between the
BeagleBone and the switch.
>
> Should I not be able to do that? It should be fixed at 100Mbps without
> autoneg, end of story? Because in the current configuration it feels
> like the fixed-link settings are more a suggestion than a rule...
>
It should describe the hardware configuration, of course. It is
incorrect to describe one side of a copper PHY connection as fixed-link
and the other as having a phy-handle, and it sounds like this is what
you're doing. We need to see the device tree binding for eth0, and
maybe a picture of your setup if that is possible. How do you connect
the switch board to the BeagleBone? Is it an RJ45 cable or some sort of
PCIe-style connector with fingers for an SGMII SERDES lane, in which the
board is plugged?
The device tree says SGMII, the behavior says RJ45.
