This patchset add mt8195 iommu support.
mt8195 have 3 IOMMU HWs. 2 IOMMU HW is for multimedia, and 1 IOMMU HW is
for infra-master, like PCIe/USB.
About the 2 MM IOMMU HW, something like this:
IOMMU(VDO) IOMMU(VPP)
| |
SMI_COMMON(VDO) SMI_COMMON(VPP)
--------------- ----------------
| | ... | | ...
larb0 larb2 ... larb1 larb3 ...
these two MM IOMMU HW share a pgtable.
About the INFRA IOMMU, it don't have larbs, the master connects the iommu
directly. It use a independent pgtable.
Also, mt8195 IOMMU bank supports.Normally the IOMMU register size only
is 0x1000. In this IOMMU HW, the register size is 5 * 0x1000. each 0x1000
is a bank. the banks' register look like this:
----------------------------------------
|bank0 | bank1 | bank2 | bank3 | bank4|
----------------------------------------
|global |
|control| null
|regs |
-----------------------------------------
|bank |bank |bank |bank |bank |
|regs |regs |regs |regs |regs |
| | | | | |
-----------------------------------------
All the banks share some global control registers, and each bank have its
special bank registers, like pgtable base register, tlb operation registers,
the fault status registers.
In mt8195, we enable this bank feature for infra iommu, We put PCIe in bank0
and USB in bank4. they have independent pgtable.
patch[1..19]: support mt8195 iommu.
patch[20..29]: support bank feature.
TODO: there is another APU_IOMMU in mt8195, this should depend on APU patches.
thus, we need add that feature after that.
Change note:
v2: 1) Base on v5.14-rc1.
2) Fix build fail for arm32.
3) Fix dt-binding issue from Rob.
4) Fix the bank issue when tlb flush. v1 always use bank->base.
5) Adjust devlink with smi-common since the node may be smi-sub-common.
6) other changes: like reword some commit message(removing many
"This patch..."); seperate serveral patches.
v1: https://lore.kernel.org/linux-mediatek/20210630023504.18177-1-yong.wu@xxxxxxxxxxxx/
Base on v5.13-rc1.
Yong Wu (29):
dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
dt-bindings: mediatek: mt8195: Add binding for infra IOMMU
iommu/mediatek: Fix 2 HW sharing pgtable issue
iommu/mediatek: Adapt sharing and non-sharing pgtable case
iommu/mediatek: Add 12G~16G support for multi domains
iommu/mediatek: Add a flag DCM_DISABLE
iommu/mediatek: Add a flag NON_STD_AXI
iommu/mediatek: Remove for_each_m4u in tlb_sync_all
iommu/mediatek: Add tlb_lock in tlb_flush_all
iommu/mediatek: Remove the granule in the tlb flush
iommu/mediatek: Always pm_runtime_get while tlb flush
iommu/mediatek: Always enable output PA over 32bits in isr
iommu/mediatek: Add SUB_COMMON_3BITS flag
iommu/mediatek: Add IOMMU_TYPE flag
iommu/mediatek: Contain MM IOMMU flow with the MM TYPE
iommu/mediatek: Adjust device link when it is sub-common
iommu/mediatek: Add infra iommu support
iommu/mediatek: Add PCIe support
iommu/mediatek: Add mt8195 support
iommu/mediatek: Only adjust code about register base
iommu/mediatek: Just move code position in hw_init
iommu/mediatek: Add mtk_iommu_bank_data structure
iommu/mediatek: Initialise bank HW for each a bank
iommu/mediatek: Add bank_nr and bank_enable
iommu/mediatek: Change the domid to iova_region_id
iommu/mediatek: Get the proper bankid for multi banks
iommu/mediatek: Initialise/Remove for multi bank dev
iommu/mediatek: Backup/restore regsiters for multi banks
iommu/mediatek: mt8195: Enable multi banks for infra iommu
.../bindings/iommu/mediatek,iommu.yaml | 20 +-
drivers/iommu/mtk_iommu.c | 792 ++++++++++++------
drivers/iommu/mtk_iommu.h | 55 +-
.../dt-bindings/memory/mt8195-memory-port.h | 408 +++++++++
include/dt-bindings/memory/mtk-memory-port.h | 2 +
5 files changed, 1010 insertions(+), 267 deletions(-)
create mode 100644 include/dt-bindings/memory/mt8195-memory-port.h
--
2.18.0
