Andrew, On Fri, 2021-07-23 at 23:01 +0530, Prasanna Vengateshan wrote: > Added support for Microchip LAN937x T1 phy driver. The sequence of > initialization is used commonly for both LAN87xx and LAN937x > drivers. The new initialization sequence is an improvement to > existing LAN87xx and it is shared with LAN937x. > > Also relevant comments are added in the existing code and existing > soft-reset customized code has been replaced with > genphy_soft_reset(). > > access_ereg_clr_poll_timeout() API is introduced for polling phy > bank write and this is linked with PHYACC_ATTR_MODE_POLL. > > Finally introduced function table for LAN937X_T1_PHY_ID along with > microchip_t1_phy_driver struct. > > Signed-off-by: Prasanna Vengateshan <prasanna.vengateshan@xxxxxxxxxxxxx> > --- > drivers/net/phy/microchip_t1.c | 319 +++++++++++++++++++++++++++------ > 1 file changed, 260 insertions(+), 59 deletions(-) > > diff --git a/drivers/net/phy/microchip_t1.c b/drivers/net/phy/microchip_t1.c > index 4dc00bd5a8d2..a3f1b5d123ce 100644 > --- a/drivers/net/phy/microchip_t1.c > +++ b/drivers/net/phy/microchip_t1.c > @@ -30,15 +30,53 @@ > #define PHYACC_ATTR_MODE_READ 0 > #define PHYACC_ATTR_MODE_WRITE 1 > #define PHYACC_ATTR_MODE_MODIFY 2 > +#define PHYACC_ATTR_MODE_POLL 3 > > #define PHYACC_ATTR_BANK_SMI 0 > #define PHYACC_ATTR_BANK_MISC 1 > #define PHYACC_ATTR_BANK_PCS 2 > #define PHYACC_ATTR_BANK_AFE 3 > +#define PHYACC_ATTR_BANK_DSP 4 > #define PHYACC_ATTR_BANK_MAX 7 Are there any items that need a change in this patch? It will be helpful for me to include them in the next version. Thanks. Prasanna V
