Hi Marc, On 10/08/21 6:03 pm, Marc Zyngier wrote: > On Mon, 09 Aug 2021 15:58:38 +0100, > Kishon Vijay Abraham I <kishon@xxxxxx> wrote: >> >> Hi Marc, >> >> On 09/08/21 3:09 pm, Marc Zyngier wrote: >>> On Mon, 09 Aug 2021 05:50:10 +0100, >>> Kishon Vijay Abraham I <kishon@xxxxxx> wrote: >>>> >>>> Hi Marc, >>>> >>>> On 04/08/21 8:43 pm, Marc Zyngier wrote: >>>>> On Wed, 04 Aug 2021 14:29:11 +0100, >>>>> Kishon Vijay Abraham I <kishon@xxxxxx> wrote: >>>>>> >>>>>> Add PCI legacy interrupt support for J721E. J721E has a single HW >>>>>> interrupt line for all the four legacy interrupts INTA/INTB/INTC/INTD. >>>>>> The HW interrupt line connected to GIC is a pulse interrupt whereas >>>>>> the legacy interrupts by definition is level interrupt. In order to >>>>>> provide level interrupt functionality to edge interrupt line, PCIe >>>>>> in J721E has provided IRQ_EOI register. >>>>>> >>>>>> However due to Errata ID #i2094 ([1]), EOI feature is not enabled in HW >>>>>> and only a single pulse interrupt will be generated for every >>>>>> ASSERT_INTx/DEASSERT_INTx. >>>>> >>>>> So my earlier remark stands. If you get a single edge, how do you >>>>> handle a level that is still high after having handled the interrupt >>>>> on hardware that has this bug? >>>> >>>> Right, this hardware (J721E) has a bug but was fixed in J7200 (Patch 3/3 >>>> handles that). >>> >>> But how do you make it work with J721E? Is it even worth supporting if >>> (as I expect) it is unreliable? >> >> I've seen at-least the NVMe devices triggers the interrupts again and >> the data transfer completes. But I agree, this is unreliable. > > Then I don't think you should add INTx support for this system. It is > bound to be a support burden, and will reflect badly on the whole > platform. Focusing on J7200 is probably the best thing to do. Okay, will drop this patch from the series and have INTx support only for J7200. Thanks Kishon
