Changes in v5:
* Re ordered PCIe, PHY nodes in Soc and board specific dtsi files.
* Removed ref_clk entry in current patch [PATCH v4 P4/4].
* I will add ref clk entry in suspend/ resume commits.
* Added boolean flag in Soc specific dtsi file to differentiate
SM8250 and SC7280 platforms. based on boolean flag, platforms will handle
the pipe clk handling.
Changes in v4 as suggested by Bjorn:
* Changed pipe clk mux name as gcc_pcie_1_pipe_clk_src.
* Changed pipe_ext_src as phy_pipe_clk.
* Updated commit message for [PATCH v4 4/4].
Changes in v3:
* Changed pipe clock names in dt bindings as pipe_mux and phy_pipe.
* Moved reset and NVMe GPIO pin configs into board specific file.
* Updated pipe clk mux commit message.
Changes in v2:
* Moved pcie pin control settings into IDP file.
* Replaced pipe_clk_src with pipe_clk_mux in pcie driver
* Included pipe clk mux setting change set in this series
Prasad Malisetty (4):
dt-bindings: pci: qcom: Document PCIe bindings for SC7280
arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes
arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board
PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280
.../devicetree/bindings/pci/qcom,pcie.txt | 17 +++
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 38 +++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 126 +++++++++++++++++++++
drivers/pci/controller/dwc/pcie-qcom.c | 18 +++
4 files changed, 199 insertions(+)
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