> Subject: [PATCH v2 02/18] soc: imx: gpcv2: Turn domain->pgc into bitfield
>
> From: Marek Vasut <marex@xxxxxxx>
>
> There is currently the MX8MM GPU domain, which is in fact a composite
> domain for both GPU2D and GPU3D. To correctly configure this domain, it is
> necessary to control both GPC_PGC_nCTRL(GPU_2D) and
> GPC_PGC_nCTRL(GPU_3D) at the same time. This is currently not possible.
>
> Turn the domain->pgc from value into bitfield and use for_each_set_bit() to
> iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL
> register array. This way it is possible to configure all GPC_PGC_nCTRL registers
> required in a particular domain.
>
> This is a preparatory patch, no functional change.
>
> Signed-off-by: Marek Vasut <marex@xxxxxxx>
> Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
Reviewed-by: Peng Fan <peng.fan@xxxxxxx>
> ---
> v2 (Lucas Stach):
> - rebase on top of reverted reset sequence change
> - also convert i.MX8MN domains
> ---
> drivers/soc/imx/gpcv2.c | 72 ++++++++++++++++++++++-------------------
> 1 file changed, 38 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> 8b7a01773aec..c7826ce92f0d 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -192,7 +192,7 @@ struct imx_pgc_domain {
> struct clk_bulk_data *clks;
> int num_clks;
>
> - unsigned int pgc;
> + unsigned long pgc;
>
> const struct {
> u32 pxx;
> @@ -220,7 +220,7 @@ to_imx_pgc_domain(struct generic_pm_domain
> *genpd) static int imx_pgc_power_up(struct generic_pm_domain *genpd)
> {
> struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
> - u32 reg_val;
> + u32 reg_val, pgc;
> int ret;
>
> ret = pm_runtime_get_sync(domain->dev); @@ -264,8 +264,10 @@
> static int imx_pgc_power_up(struct generic_pm_domain *genpd)
> }
>
> /* disable power control */
> - regmap_clear_bits(domain->regmap,
> GPC_PGC_CTRL(domain->pgc),
> - GPC_PGC_CTRL_PCR);
> + for_each_set_bit(pgc, &domain->pgc, 32) {
> + regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc),
> + GPC_PGC_CTRL_PCR);
> + }
> }
>
> /* delay for reset to propagate */
> @@ -311,7 +313,7 @@ static int imx_pgc_power_up(struct
> generic_pm_domain *genpd) static int imx_pgc_power_down(struct
> generic_pm_domain *genpd) {
> struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
> - u32 reg_val;
> + u32 reg_val, pgc;
> int ret;
>
> /* Enable reset clocks for all devices in the domain */ @@ -338,8
> +340,10 @@ static int imx_pgc_power_down(struct generic_pm_domain
> *genpd)
>
> if (domain->bits.pxx) {
> /* enable power control */
> - regmap_update_bits(domain->regmap,
> GPC_PGC_CTRL(domain->pgc),
> - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
> + for_each_set_bit(pgc, &domain->pgc, 32) {
> + regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc),
> + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
> + }
>
> /* request the domain to power down */
> regmap_update_bits(domain->regmap,
> GPC_PU_PGC_SW_PDN_REQ, @@ -389,7 +393,7 @@ static const struct
> imx_pgc_domain imx7_pgc_domains[] = {
> .map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
> },
> .voltage = 1000000,
> - .pgc = IMX7_PGC_MIPI,
> + .pgc = BIT(IMX7_PGC_MIPI),
> },
>
> [IMX7_POWER_DOMAIN_PCIE_PHY] = {
> @@ -401,7 +405,7 @@ static const struct imx_pgc_domain
> imx7_pgc_domains[] = {
> .map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
> },
> .voltage = 1000000,
> - .pgc = IMX7_PGC_PCIE,
> + .pgc = BIT(IMX7_PGC_PCIE),
> },
>
> [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
> @@ -413,7 +417,7 @@ static const struct imx_pgc_domain
> imx7_pgc_domains[] = {
> .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
> },
> .voltage = 1200000,
> - .pgc = IMX7_PGC_USB_HSIC,
> + .pgc = BIT(IMX7_PGC_USB_HSIC),
> },
> };
>
> @@ -448,7 +452,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
> .pxx = IMX8M_MIPI_SW_Pxx_REQ,
> .map = IMX8M_MIPI_A53_DOMAIN,
> },
> - .pgc = IMX8M_PGC_MIPI,
> + .pgc = BIT(IMX8M_PGC_MIPI),
> },
>
> [IMX8M_POWER_DOMAIN_PCIE1] = {
> @@ -459,7 +463,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
> .pxx = IMX8M_PCIE1_SW_Pxx_REQ,
> .map = IMX8M_PCIE1_A53_DOMAIN,
> },
> - .pgc = IMX8M_PGC_PCIE1,
> + .pgc = BIT(IMX8M_PGC_PCIE1),
> },
>
> [IMX8M_POWER_DOMAIN_USB_OTG1] = {
> @@ -470,7 +474,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
> .pxx = IMX8M_OTG1_SW_Pxx_REQ,
> .map = IMX8M_OTG1_A53_DOMAIN,
> },
> - .pgc = IMX8M_PGC_OTG1,
> + .pgc = BIT(IMX8M_PGC_OTG1),
> },
>
> [IMX8M_POWER_DOMAIN_USB_OTG2] = {
> @@ -481,7 +485,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
> .pxx = IMX8M_OTG2_SW_Pxx_REQ,
> .map = IMX8M_OTG2_A53_DOMAIN,
> },
> - .pgc = IMX8M_PGC_OTG2,
> + .pgc = BIT(IMX8M_PGC_OTG2),
> },
>
> [IMX8M_POWER_DOMAIN_DDR1] = {
> @@ -492,7 +496,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
> .pxx = IMX8M_DDR1_SW_Pxx_REQ,
> .map = IMX8M_DDR2_A53_DOMAIN,
> },
> - .pgc = IMX8M_PGC_DDR1,
> + .pgc = BIT(IMX8M_PGC_DDR1),
> },
>
> [IMX8M_POWER_DOMAIN_GPU] = {
> @@ -505,7 +509,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
> .hskreq = IMX8M_GPU_HSK_PWRDNREQN,
> .hskack = IMX8M_GPU_HSK_PWRDNACKN,
> },
> - .pgc = IMX8M_PGC_GPU,
> + .pgc = BIT(IMX8M_PGC_GPU),
> },
>
> [IMX8M_POWER_DOMAIN_VPU] = {
> @@ -518,7 +522,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
> .hskreq = IMX8M_VPU_HSK_PWRDNREQN,
> .hskack = IMX8M_VPU_HSK_PWRDNACKN,
> },
> - .pgc = IMX8M_PGC_VPU,
> + .pgc = BIT(IMX8M_PGC_VPU),
> },
>
> [IMX8M_POWER_DOMAIN_DISP] = {
> @@ -531,7 +535,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
> .hskreq = IMX8M_DISP_HSK_PWRDNREQN,
> .hskack = IMX8M_DISP_HSK_PWRDNACKN,
> },
> - .pgc = IMX8M_PGC_DISP,
> + .pgc = BIT(IMX8M_PGC_DISP),
> },
>
> [IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
> @@ -542,7 +546,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
> .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
> .map = IMX8M_MIPI_CSI1_A53_DOMAIN,
> },
> - .pgc = IMX8M_PGC_MIPI_CSI1,
> + .pgc = BIT(IMX8M_PGC_MIPI_CSI1),
> },
>
> [IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
> @@ -553,7 +557,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
> .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
> .map = IMX8M_MIPI_CSI2_A53_DOMAIN,
> },
> - .pgc = IMX8M_PGC_MIPI_CSI2,
> + .pgc = BIT(IMX8M_PGC_MIPI_CSI2),
> },
>
> [IMX8M_POWER_DOMAIN_PCIE2] = {
> @@ -564,7 +568,7 @@ static const struct imx_pgc_domain
> imx8m_pgc_domains[] = {
> .pxx = IMX8M_PCIE2_SW_Pxx_REQ,
> .map = IMX8M_PCIE2_A53_DOMAIN,
> },
> - .pgc = IMX8M_PGC_PCIE2,
> + .pgc = BIT(IMX8M_PGC_PCIE2),
> },
> };
>
> @@ -627,7 +631,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
> .pxx = IMX8MM_PCIE_SW_Pxx_REQ,
> .map = IMX8MM_PCIE_A53_DOMAIN,
> },
> - .pgc = IMX8MM_PGC_PCIE,
> + .pgc = BIT(IMX8MM_PGC_PCIE),
> },
>
> [IMX8MM_POWER_DOMAIN_OTG1] = {
> @@ -638,7 +642,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
> .pxx = IMX8MM_OTG1_SW_Pxx_REQ,
> .map = IMX8MM_OTG1_A53_DOMAIN,
> },
> - .pgc = IMX8MM_PGC_OTG1,
> + .pgc = BIT(IMX8MM_PGC_OTG1),
> },
>
> [IMX8MM_POWER_DOMAIN_OTG2] = {
> @@ -649,7 +653,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
> .pxx = IMX8MM_OTG2_SW_Pxx_REQ,
> .map = IMX8MM_OTG2_A53_DOMAIN,
> },
> - .pgc = IMX8MM_PGC_OTG2,
> + .pgc = BIT(IMX8MM_PGC_OTG2),
> },
>
> [IMX8MM_POWER_DOMAIN_GPUMIX] = {
> @@ -662,7 +666,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
> .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
> .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
> },
> - .pgc = IMX8MM_PGC_GPUMIX,
> + .pgc = BIT(IMX8MM_PGC_GPUMIX),
> },
>
> [IMX8MM_POWER_DOMAIN_GPU] = {
> @@ -675,7 +679,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
> .hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
> .hskack = IMX8MM_GPU_HSK_PWRDNACKN,
> },
> - .pgc = IMX8MM_PGC_GPU2D,
> + .pgc = BIT(IMX8MM_PGC_GPU2D),
> },
>
> [IMX8MM_POWER_DOMAIN_VPUMIX] = {
> @@ -688,7 +692,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
> .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN,
> .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
> },
> - .pgc = IMX8MM_PGC_VPUMIX,
> + .pgc = BIT(IMX8MM_PGC_VPUMIX),
> },
>
> [IMX8MM_POWER_DOMAIN_VPUG1] = {
> @@ -699,7 +703,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
> .pxx = IMX8MM_VPUG1_SW_Pxx_REQ,
> .map = IMX8MM_VPUG1_A53_DOMAIN,
> },
> - .pgc = IMX8MM_PGC_VPUG1,
> + .pgc = BIT(IMX8MM_PGC_VPUG1),
> },
>
> [IMX8MM_POWER_DOMAIN_VPUG2] = {
> @@ -710,7 +714,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
> .pxx = IMX8MM_VPUG2_SW_Pxx_REQ,
> .map = IMX8MM_VPUG2_A53_DOMAIN,
> },
> - .pgc = IMX8MM_PGC_VPUG2,
> + .pgc = BIT(IMX8MM_PGC_VPUG2),
> },
>
> [IMX8MM_POWER_DOMAIN_VPUH1] = {
> @@ -721,7 +725,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
> .pxx = IMX8MM_VPUH1_SW_Pxx_REQ,
> .map = IMX8MM_VPUH1_A53_DOMAIN,
> },
> - .pgc = IMX8MM_PGC_VPUH1,
> + .pgc = BIT(IMX8MM_PGC_VPUH1),
> },
>
> [IMX8MM_POWER_DOMAIN_DISPMIX] = {
> @@ -734,7 +738,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
> .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN,
> .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
> },
> - .pgc = IMX8MM_PGC_DISPMIX,
> + .pgc = BIT(IMX8MM_PGC_DISPMIX),
> },
>
> [IMX8MM_POWER_DOMAIN_MIPI] = {
> @@ -745,7 +749,7 @@ static const struct imx_pgc_domain
> imx8mm_pgc_domains[] = {
> .pxx = IMX8MM_MIPI_SW_Pxx_REQ,
> .map = IMX8MM_MIPI_A53_DOMAIN,
> },
> - .pgc = IMX8MM_PGC_MIPI,
> + .pgc = BIT(IMX8MM_PGC_MIPI),
> },
> };
>
> @@ -812,7 +816,7 @@ static const struct imx_pgc_domain
> imx8mn_pgc_domains[] = {
> .pxx = IMX8MN_OTG1_SW_Pxx_REQ,
> .map = IMX8MN_OTG1_A53_DOMAIN,
> },
> - .pgc = IMX8MN_PGC_OTG1,
> + .pgc = BIT(IMX8MN_PGC_OTG1),
> },
>
> [IMX8MN_POWER_DOMAIN_GPUMIX] = {
> @@ -825,7 +829,7 @@ static const struct imx_pgc_domain
> imx8mn_pgc_domains[] = {
> .hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
> .hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
> },
> - .pgc = IMX8MN_PGC_GPUMIX,
> + .pgc = BIT(IMX8MN_PGC_GPUMIX),
> },
> };
>
> --
> 2.30.2
