On Thu, 05 Aug 2021 08:17:14 +0100, Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx> wrote: > > On 04/08/2021 23:30, Sam Protsenko wrote: > >>> > >>> Nice catch! Actually there is an error (typo?) in SoC's TRM, saying > >>> that Virtual Interface Control Register starts at 0x3000 offset (from > >>> 0x12a00000), where it obviously should be 0x4000, that's probably > >>> where this dts error originates from. Btw, I'm also seeing the same > >>> error in exynos7.dtsi. > >> > >> What's the error exactly? The "Virtual interface control register" > >> offset (3rd region) is set properly to 0x4000 on Exynos7. Also one for > >> the Exynos5433 looks correct. > >> > > > > The issue is that 2nd region's size is 0x1000, but it must be 0x2000. > > It's defined by GIC-400 architecture, as I understand. Please look at > > [1], table 3-1 has very specific offsets and sizes for each functional > > block, and each particular SoC must adhere to that spec. So having > > 0x1000 for 2nd region can't be correct. And because exynos7.dtsi has > > GIC-400 as well, and 0x1000 is specified there for 2nd region size > > too, so I presume there is the same mistake there. > > I understand, the range length has indeed same mistake. However it does > not matter that much There are no registers pass 0x10C (so pass 0x1000). > This address space is not used. I have no idea which spec you are looking at, but the GICv2 architecture (of which GIC400 is an implementation) definitely has a register in the second 4kB page of the CPU interface. It contains the GICC_DIR register, which is used to deactivate an interrupt when EOIMode==1. Linux actively uses it when started at EL2. M. -- Without deviation from the norm, progress is not possible.
