Em Mon, 2 Aug 2021 16:50:53 -0600
Rob Herring <robh@xxxxxxxxxx> escreveu:
> On Thu, Jul 29, 2021 at 09:03:37PM +0200, Mauro Carvalho Chehab wrote:
> > Em Thu, 29 Jul 2021 09:20:15 -0600
> > Rob Herring <robh@xxxxxxxxxx> escreveu:
> >
> >
> > Ok. If I understood your review, the schema will then be:
> >
> > pcie@f4000000 {
> > compatible = "hisilicon,kirin970-pcie";
> > reg = <0x0 0xf4000000 0x0 0x1000000>,
> > <0x0 0xfc180000 0x0 0x1000>,
> > <0x0 0xf5000000 0x0 0x2000>;
> > reg-names = "dbi", "apb", "config";
> > bus-range = <0x0 0x1>;
> > msi-parent = <&its_pcie>;
> > #address-cells = <3>;
> > #size-cells = <2>;
> > device_type = "pci";
> > phys = <&pcie_phy>;
> > ranges = <0x02000000 0x0 0x00000000
> > 0x0 0xf6000000
> > 0x0 0x02000000>;
> > num-lanes = <1>;
> > #interrupt-cells = <1>;
> > interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
> > interrupt-names = "msi";
> > interrupt-map-mask = <0 0 0 7>;
> > interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> > <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> > <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> > <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
> > reset-gpios = <&gpio7 0 0>;
> >
> > pcie@0 { // Lane 0: upstream
> > reg = <0 0 0 0 0>;
> > compatible = "pciclass,0604";
> > device_type = "pci";
> > #address-cells = <3>;
> > #size-cells = <2>;
> > hisilicon,clken-gpios = <&gpio27 3 0 >, <&gpio17 0 0 >, <&gpio20 6 0 >;
>
> Up one more level.
Yeah. This is at the upper level at the newer series:
[PATCH v2 3/4] dt-bindings: PCI: kirin: Add support for Kirin970
https://lore.kernel.org/lkml/93a42a6317eed3b0eb6a35b6d4c484e106cb2793.1627637448.git.mchehab+huawei@xxxxxxxxxx/
> > ranges;
> >
> > pcie@1,0 { // Lane 4: M.2
> > reg = <0x800 0 0 0 0>;
> > compatible = "pciclass,0604";
> > device_type = "pci";
> > reset-gpios = <&gpio3 1 0>;
> > #address-cells = <3>;
> > #size-cells = <2>;
> > ranges;
> > };
> >
> > pcie@5,0 { // Lane 5: Mini PCIe
> > reg = <0x2800 0 0 0 0>;
> > compatible = "pciclass,0604";
> > device_type = "pci";
> > reset-gpios = <&gpio27 4 0 >;
> > #address-cells = <3>;
> > #size-cells = <2>;
> > ranges;
> > };
> >
> > pcie@7,0 { // Lane 7: Ethernet
>
> Port 7 is lane 6 and Port 9 is lane 7. So I think it should be 'Lane 6'.
True. I'll fix it on v3.
>
> > reg = <0x3800 0 0 0 0>;
> > compatible = "pciclass,0604";
> > device_type = "pci";
> > reset-gpios = <&gpio25 2 0 >;
> > #address-cells = <3>;
> > #size-cells = <2>;
> > ranges;
> > };
> > };
> > };
> > };
> >
> > Right?
> >
> > After updating the dt-schema from your git tree, the above doesn't
> > generate warnings anymore.
> >
> > Thanks,
> > Mauro
> >
Thanks,
Mauro
