On Fri, 30 Jul 2021 at 18:22, Krzysztof Kozlowski
<krzysztof.kozlowski@xxxxxxxxxxxxx> wrote:
>
> On 30/07/2021 16:49, Sam Protsenko wrote:
> > Add Samsung Exynos850 SoC specific data to enable pinctrl support for
> > all platforms based on Exynos850.
> >
> > Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
> > ---
> > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 129 ++++++++++++++++++
> > drivers/pinctrl/samsung/pinctrl-exynos.h | 29 ++++
> > drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
> > drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
> > 4 files changed, 161 insertions(+)
> >
> > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> > index b6e56422a700..9c71ff84ba7e 100644
> > --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> > +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> > @@ -40,6 +40,24 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
> > .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
> > };
> >
> > +/*
> > + * Bank type for non-alive type. Bit fields:
> > + * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4
> > + */
> > +static struct samsung_pin_bank_type exynos850_bank_type_off = {
> > + .fld_width = { 4, 1, 4, 4, 2, 4, },
> > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
> > +};
> > +
> > +/*
> > + * Bank type for alive type. Bit fields:
> > + * CON: 4, DAT: 1, PUD: 4, DRV: 4
> > + */
> > +static struct samsung_pin_bank_type exynos850_bank_type_alive = {
> > + .fld_width = { 4, 1, 4, 4, },
> > + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
> > +};
> > +
> > /* Pad retention control code for accessing PMU regmap */
> > static atomic_t exynos_shared_retention_refcnt;
> >
> > @@ -422,3 +440,114 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = {
> > .ctrl = exynos7_pin_ctrl,
> > .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl),
> > };
> > +
> > +/* pin banks of exynos850 pin-controller 0 (ALIVE) */
> > +static struct samsung_pin_bank_data exynos850_pin_banks0[] = {
> > + /* Must start with EINTG banks, ordered by EINT group number. */
> > + EXYNOS9_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
>
> Why EXYNOS9 not EXYNOS850? Is it really shared with 96xx, 98xx and 9x0
> series?
>
Yeah, I double checked and those macros are actually used for 96xx
SoCs. So I suggest we leave it as is, as it seems to be related to the
whole architecture series, not only to Exynos850.
> > + EXYNOS9_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
> > + EXYNOS9_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
> > + EXYNOS9_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
> > + EXYNOS9_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10),
> > + EXYNOS9_PIN_BANK_EINTN(3, 0x0A0, "gpq0"),
> > +};
> > +
> > +/* pin banks of exynos850 pin-controller 1 (CMGP) */
> > +static struct samsung_pin_bank_data exynos850_pin_banks1[] = {
> > + /* Must start with EINTG banks, ordered by EINT group number. */
> > + EXYNOS9_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00),
> > + EXYNOS9_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04),
> > + EXYNOS9_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08),
> > + EXYNOS9_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C),
> > + EXYNOS9_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10),
> > + EXYNOS9_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14),
> > + EXYNOS9_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18),
> > + EXYNOS9_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C),
> > +};
> > +
> > +/* pin banks of exynos850 pin-controller 2 (AUD) */
> > +static struct samsung_pin_bank_data exynos850_pin_banks2[] = {
> > + /* Must start with EINTG banks, ordered by EINT group number. */
> > + EXYNOS9_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
> > + EXYNOS9_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04),
> > +};
> > +
> > +/* pin banks of exynos850 pin-controller 3 (HSI) */
> > +static struct samsung_pin_bank_data exynos850_pin_banks3[] = {
> > + /* Must start with EINTG banks, ordered by EINT group number. */
> > + EXYNOS9_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00),
> > +};
> > +
> > +/* pin banks of exynos850 pin-controller 4 (CORE) */
> > +static struct samsung_pin_bank_data exynos850_pin_banks4[] = {
> > + /* Must start with EINTG banks, ordered by EINT group number. */
> > + EXYNOS9_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00),
> > + EXYNOS9_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04),
> > +};
> > +
> > +/* pin banks of exynos850 pin-controller 5 (PERI) */
> > +static struct samsung_pin_bank_data exynos850_pin_banks5[] = {
> > + /* Must start with EINTG banks, ordered by EINT group number. */
> > + EXYNOS9_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00),
> > + EXYNOS9_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04),
> > + EXYNOS9_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08),
> > + EXYNOS9_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0C),
> > + EXYNOS9_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10),
> > + EXYNOS9_PIN_BANK_EINTG(8, 0x0A0, "gpg2", 0x14),
> > + EXYNOS9_PIN_BANK_EINTG(1, 0x0C0, "gpg3", 0x18),
> > + EXYNOS9_PIN_BANK_EINTG(3, 0x0E0, "gpc0", 0x1C),
> > + EXYNOS9_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20),
> > +};
> > +
> > +static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = {
> > + {
> > + /* pin-controller instance 0 ALIVE data */
> > + .pin_banks = exynos850_pin_banks0,
> > + .nr_banks = ARRAY_SIZE(exynos850_pin_banks0),
> > + .eint_gpio_init = exynos_eint_gpio_init,
> > + .eint_wkup_init = exynos_eint_wkup_init,
> > + .suspend = exynos_pinctrl_suspend,
> > + .resume = exynos_pinctrl_resume,
>
> I guess retention registers will follow sometime later.
>
Good point, never noticed retention control is needed for
suspend/resume to work properly. I will remove suspend/resume ops in
v2, and PM support will be sent later.
> Best regards,
> Krzysztof
