Add the requisite nodes to the rk3568 device tree to enable the usb2
device controllers.
Includes the usb2phy nodes, usb2phy grf nodes, and usb2 controller
nodes.
Signed-off-by: Peter Geis <pgwipeout@xxxxxxxxx>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 97 ++++++++++++++++++++++++
1 file changed, 97 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 322971318d5a..ea254a58fc01 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -200,6 +200,50 @@ gic: interrupt-controller@fd400000 {
msi-controller;
};
+ usb_host0_ehci: usb@fd800000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xfd800000 0x0 0x40000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
+ <&cru PCLK_USB>, <&usb2phy1>;
+ phys = <&u2phy1_otg>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@fd840000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xfd840000 0x0 0x40000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
+ <&cru PCLK_USB>, <&usb2phy1>;
+ phys = <&u2phy1_otg>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host1_ehci: usb@fd880000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xfd880000 0x0 0x40000>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
+ <&cru PCLK_USB>, <&usb2phy1>;
+ phys = <&u2phy1_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host1_ohci: usb@fd8c0000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xfd8c0000 0x0 0x40000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
+ <&cru PCLK_USB>, <&usb2phy1>;
+ phys = <&u2phy1_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
pmugrf: syscon@fdc20000 {
compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xfdc20000 0x0 0x10000>;
@@ -210,6 +254,16 @@ grf: syscon@fdc60000 {
reg = <0x0 0xfdc60000 0x0 0x10000>;
};
+ usb2phy0_grf: syscon@fdca0000 {
+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
+ reg = <0x0 0xfdca0000 0x0 0x8000>;
+ };
+
+ usb2phy1_grf: syscon@fdca8000 {
+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
+ reg = <0x0 0xfdca8000 0x0 0x8000>;
+ };
+
pmucru: clock-controller@fdd00000 {
compatible = "rockchip,rk3568-pmucru";
reg = <0x0 0xfdd00000 0x0 0x1000>;
@@ -738,6 +792,49 @@ saradc: saradc@fe720000 {
status = "disabled";
};
+ usb2phy0: usb2-phy@fe8a0000 {
+ compatible = "rockchip,rk3568-usb2phy";
+ reg = <0x0 0xfe8a0000 0x0 0x10000>;
+ clocks = <&pmucru CLK_USBPHY0_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "usb480m_phy";
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,usbgrf = <&usb2phy0_grf>;
+ status = "disabled";
+
+ u2phy0_host: host-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy0_otg: otg-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ usb2phy1: usb2-phy@fe8b0000 {
+ compatible = "rockchip,rk3568-usb2phy";
+ reg = <0x0 0xfe8b0000 0x0 0x10000>;
+ clocks = <&pmucru CLK_USBPHY1_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,usbgrf = <&usb2phy1_grf>;
+ status = "disabled";
+
+ u2phy1_host: host-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy1_otg: otg-port {
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3568-pinctrl";
rockchip,grf = <&grf>;
--
2.25.1
