On Wed, 28 Jul 2021 at 13:19, Michael Walle <michael@xxxxxxxx> wrote: > Am 2021-07-28 12:59, schrieb Emil Renner Berthing: > > On Wed, 28 Jul 2021 at 11:49, Michael Walle <michael@xxxxxxxx> wrote: > >> Hi Drew, > >> Am 2021-07-27 07:28, schrieb Drew Fustini: > >> [..] > >> >> > > Drew please look at drivers/gpio/gpio-ftgpio010.c for an example > >> >> > > of GPIO_GENERIC calling bgpio_init() in probe(). > >> >> > > >> >> > Thank you for the suggestion. However, I am not sure that will work for > >> >> > this SoC. > >> >> > > >> >> > The GPIO registers are described in section 12 of JH7100 datasheet [1] > >> >> > and I don't think they fit the expectation of gpio-mmio.c because there > >> >> > is a seperate register for each GPIO line for output data value and > >> >> > output enable. > >> >> > > >> >> > There are 64 output data config registers which are 4 bytes wide. There > >> >> > are 64 output enable config registers which are 4 bytes wide too. Output > >> >> > data and output enable registers for a given GPIO pad are contiguous. > >> >> > GPIO0_DOUT_CFG is 0x50 and GPIO0_DOEN_CFG is 0x54 while GPIO1_DOUT_CFG > >> >> > is 0x58 and GPIO1_DOEN_CFG is 0x5C. The stride between GPIO pads is > >> >> > effectively 8, which yields the formula: GPIOn_DOUT_CFG is 0x50+8n. > >> >> > Similarly, GPIO0_DOEN_CFG is 0x54 and thus GPIOn_DOEN_CFG is 0x54+8n. > >> >> > > >> >> > However, GPIO input data does use just one bit for each line. GPIODIN_0 > >> >> > at 0x48 covers GPIO[31:0] and GPIODIN_1 at 0x4c covers GPIO[63:32]. > >> > >> Mh, I'm not sure I'm understanding the datasheet/registers. _DOUT_CFG > >> and _DOEN_CFG seem to specify the pad where this GPIO is mapped to. > >> Shouldn't this be some kind of pinctrl then? Apparently you can map > >> any GPIO number to any output pad, no? Or at least to all pads > >> which are described in Table 11-2. What happens if two different GPIOs > >> are mapped to the same pad? Bit 31 in these _CFG seems to be an invert > >> bit, but what does it invert? > >> > >> Similar, the input GPIOs are connected to an output pad by all the > >> GPI_*_CFG registers. > >> > >> To me it seems, that there two multiplexers for each GPIO, where > >> you can connect any GPIOn to any input pad and output pad. Sound > >> like a huge overkill. I must be missing something here. > >> > >> But what puzzles me the most, where do I set the actual GPIO output > >> value? > > > > Yeah, it's a little confusing. The DOUT registers choose between a > > number of > > signals from various peripherals to control the output value of the > > pin. Similarly > > the DOEN registers chose between a number of signals to control the > > output > > enable of the pin. However, two of those signals are special in that > > they are > > constant 0 or constant 1. This is how you control the output value and > > output > > enable from software like a regular GPIO. > > > > You're completely right though. This ought to be managed by a proper > > pinctrl > > driver, and I'm working on one here: > > https://github.com/esmil/linux/commits/beaglev-pinctrl > > Ahh, I see. So for the non-gpio function you have to set a value other > than 0 or 1, correct? > > And as an implementation detail you have to set the corresponding OE > pin if the non-gpio function will need a tristate pin (or whatever). > > So, the _DOUT_CFG will actually be shared between the pinctrl and the > gpio driver, right? (I haven't done anything with pinctrl, so this might > be a stupid question). No, not a stupid question. You've got that exactly right. /Emil
