On Wed, Jul 28, 2021 at 7:13 AM Michal Simek <michal.simek@xxxxxxxxxx> wrote: > On 7/27/21 10:25 PM, Rob Herring wrote: > > On Tue, Jul 27, 2021 at 12:35 PM Gerhard Engleder > > <gerhard@xxxxxxxxxxxxxxxxxxxxx> wrote: > >> > >> On Tue, Jul 27, 2021 at 1:35 AM Rob Herring <robh+dt@xxxxxxxxxx> wrote: > >>>> +properties: > >>>> + compatible: > >>>> + oneOf: > >>> > >>> Don't need oneOf when there is only one entry. > >> > >> I will fix that. > >> > >>>> + - enum: > >>>> + - engleder,tsnep > >>> > >>> tsnep is pretty generic. Only 1 version ever? Or differences are/will > >>> be discoverable by other means. > >> > >> Differences shall be detected by flags in the registers; e.g., a flag for > >> gate control support. Anyway a version may make sense. Can you > >> point to a good reference binding with versions? I did not find a > >> network controller binding with versions. > > > > Some of the SiFive IP blocks have versions. Version numbers are the > > exception though. Ideally they would correspond to some version of > > your FPGA image. I just don't want to see 'v1' because that sounds > > made up. The above string can mean 'v1' or whatever version you want. > > I'm fine if you just add some description here about feature flag > > registers. > > Don't Xilinx design tool (vivado) force you to use IP version? > Normally all Xilinx IPs have certain version because that's the only way > how to manage it. Yes I use an IP version in the Xilinx design tool. I use it as a version of the VHDL code itself. In my case this version is not related to the hardware software interface. The goal is to keep the hardware software interface compatible, so the IP version should not be relevant. Gerhard
