On 10:46-20210720, Lokesh Vutla wrote:
>
>
> On 19/07/21 8:53 pm, Nishanth Menon wrote:
> > On 14:24-20210719, Lokesh Vutla wrote:
> >> ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
> >> signal connected to Pin 1 of J3. Add support for adding this pinmux so
> >> that pwm can be observed on pin 1 of Header J3
> >>
> >> Signed-off-by: Lokesh Vutla <lokeshvutla@xxxxxx>
> >> Signed-off-by: Vignesh Raghavendra <vigneshr@xxxxxx>
> >> ---
> >> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++
> >> 1 file changed, 12 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> >> index d3aa2901e6fd..eb0d10e6e787 100644
> >> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> >> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> >> @@ -210,6 +210,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
> >> AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
> >> >;
> >> };
> >> +
> >> + main_ecap0_pins_default: main-ecap0-pins-default {
> >> + pinctrl-single,pins = <
> >> + AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
> >> + >;
> >> + };
> >> };
> >>
> >> &mcu_uart0 {
> >> @@ -453,3 +459,9 @@ &pcie0_rc {
> >> &pcie0_ep {
> >> status = "disabled";
> >> };
> >> +
> >> +&ecap0 {
> >> + /* PWM is available on Pin 1 of header J3 */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&main_ecap0_pins_default>;
> >> +};
> >> --
> >> 2.30.0
> >>
> >
> >
> > Do the other ecap and pwm nodes need to be disabled since they may not
> > be pinned out?
>
> Sure, Ill mark other ecap and epwm nodes as disabled. After looking at
> schematics, epwm4 and 5 is pinned out on RPI header. But the header will most
> likely be used for other use-cases. Shall I mark epwm4 and epwm5 disabled as
> well with a comment with this information?
Yes, please. Thanks.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
