Hi Anand, On Fri, Jul 16, 2021 at 12:37 PM Anand Moon <linux.amoon@xxxxxxxxx> wrote: > > Add missing usb phy power node for phy mode fix below warning. > P5V0 regulator suppy input voltage range to USB host controller. low prio - typo: suppy -> supply > As descriped in the C1+ schematics, GPIO GPIOAO_5 is used to low prio - typo: descriped -> described > enable input power to USB ports, set it to Active Low. > > [ 1.253149] phy phy-c1108820.phy.0: Looking up phy-supply from device tree > [ 1.253166] phy phy-c1108820.phy.0: Looking up phy-supply property > in node /soc/cbus@c1100000/phy@8820 failed high prio: Can you please describe how I can test this patch? My concern is that previously I have tested your patch with ACTIVE_LOW and ACTIVE_HIGH polarity. In both cases USB is working and I cannot observe any change (apart from this debug message being gone). In the Odroid-C1 schematics (page 1) GPIOAO.BIT5 is connected to USB_OTG *only*. I cannot give my Acked-/Reviewed-/Tested-by without a description of how I can actually test the GPIO potion of this patch. [...] > + /* > + * signal name from schematics: PWREN - GPIOAO.BIT5 > + */ > + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; low prio: Even though it's strictly not necessary I think this is confusing to read. Since there's no "enable-active-high" property the GPIO will be considered as "active low". My suggestion is to change GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW Also if you have any extra information since you last pinged me on IRC then it would be great if you could document it. I am referring to these IRC message, where you are stating that the correct polarity should be "active high": <armoon> xdarklight I have a question on USB GPIO Polarity on Odroid C1+ <armoon> As per the https://dn.odroid.com/S805/Schematics/odroid-c1+_rev0.4_20160226.pdf <armoon> MP62551DGT-LF IC controls the power for the USB PORTS <armoon> https://www.mouser.com/datasheet/2/277/MP62550-1384050.pdf is MP62551DGT datasheet <armoon> As per the data sheet in section ORDERING INFORMATION Active enable signal is set below MP62551DGT Active High [...] > &usb1_phy { > status = "okay"; > + phy-supply = <&usb_pwr_en>; medium priority: I have raised the following concern in one of my previous emails on this topic: > The mistake I made before is considering USB VBUS as PHY power supply. > I believe the USB PHY is actually powered by the AVDD18_USB_ADC and > USB33_VDDIOH signals. See the S905 datasheet [0], page 25 > These are 1.8V and 3.3V signals while you are adding a 5V regulator. you replied with: > OK, thanks. so I don't understand what "OK, thanks" means. If it means "Martin, you are wrong" then please provide a description so I can also learn something! Best regards, Martin
