add lpsi1 and lpspi_lpcg to imx8-ss-dma.dtsi
Cc: Rob Herring <robh+dt@xxxxxxxxxx>
Cc: Sascha Hauer <kernel@xxxxxxxxxxxxxx>
Cc: Fabio Estevam <festevam@xxxxxxxxx>
Cc: Dong Aisheng <aisheng.dong@xxxxxxx>
Signed-off-by: Oliver Graute <oliver.graute@xxxxxxxxxxxxxxxxx>
---
.../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index 960a802b8b6e..98911e7a5d25 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -60,6 +60,32 @@ dma_subsys: bus@5a000000 {
status = "disabled";
};
+ lpspi1: lpspi@5a010000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a010000 0x10000>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&lpspi1_lpcg IMX_LPCG_CLK_0>,
+ <&lpspi1_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_1>;
+ status = "disabled";
+ };
+
+ lpspi1_lpcg: clock-controller@5a410000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi1_lpcg_clk",
+ "spi1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_1>;
+ };
+
uart0_lpcg: clock-controller@5a460000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a460000 0x10000>;
--
2.17.1
