On Sun, Jun 20, 2021 at 01:05:25AM +0200, Linus Walleij wrote: > This rewrites the ux500/u8500 clock bindings in YAML schema and extends them > with the PRCC reset controller. > > The bindings are a bit idiomatic but it just reflects their age, the ux500 > platform was used as guinea pig for early device tree conversion of platforms > in 2015. The new subnode for the reset controller follows the pattern of the > old bindings and adds a node with reset-cells for this. > > Cc: devicetree@xxxxxxxxxxxxxxx > Cc: Ulf Hansson <ulf.hansson@xxxxxxxxxx> > Signed-off-by: Linus Walleij <linus.walleij@xxxxxxxxxx> > --- > .../bindings/clock/stericsson,u8500-clks.yaml | 113 ++++++++++++++++++ > .../devicetree/bindings/clock/ux500.txt | 64 ---------- > .../reset/stericsson,db8500-prcc-reset.h | 51 ++++++++ > 3 files changed, 164 insertions(+), 64 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml > delete mode 100644 Documentation/devicetree/bindings/clock/ux500.txt > create mode 100644 include/dt-bindings/reset/stericsson,db8500-prcc-reset.h > > diff --git a/Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml b/Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml > new file mode 100644 > index 000000000000..b3eca95299ab > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml > @@ -0,0 +1,113 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ST-Ericsson DB8500 (U8500) clocks > + > +maintainers: > + - Ulf Hansson <ulf.hansson@xxxxxxxxxx> > + - Linus Walleij <linus.walleij@xxxxxxxxxx> > + > +description: While named "U8500 clocks" these clocks are inside the > + DB8500 digital baseband system-on-chip and its siblings such as > + DB8520. These bindings consider the clocks present in the SoC > + itself, not off-chip clocks. There are four different on-chip > + clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and > + control management unit) clocks and PRCC (peripheral reset and > + clock controller) clocks. > + > +properties: > + compatible: > + oneOf: > + - const: stericsson,u8500-clks > + - const: stericsson,u8540-clks > + - const: stericsson,u9540-clks enum instead of oneOf+const > + > + reg: > + items: > + - description: PRCC 1 register area > + - description: PRCC 2 register area > + - description: PRCC 3 register area > + - description: PRCC 5 register area > + - description: PRCC 6 register area > + > + prcmu-clock: > + description: A subnode with one clock cell for PRCMU (power, reset, control > + management unit) clocks. The cell indicates which PRCMU clock in the > + prcmu-clock node the consumer wants to use. > + type: object > + > + properties: > + '#clock-cells': > + const: 1 > + > + additionalProperties: false > + > + prcc-periph-clock: > + description: A subnode with two clock cells for PRCC (peripheral > + reset and clock controller) peripheral clocks. The first cell indicates > + which PRCC block the consumer wants to use, possible values are 1, 2, 3, > + 5, 6. The second cell indicates which clock inside the PRCC block it > + wants, possible values are 0 thru 31. > + type: object > + > + properties: > + '#clock-cells': > + const: 2 > + > + additionalProperties: false > + > + prcc-kernel-clock: > + description: A subnode with two clock cells for PRCC (peripheral reset > + and clock controller) kernel clocks. The first cell indicates which PRCC > + block the consumer wants to use, possible values are 1, 2, 3, 5, 6. The > + second cell indicates which clock inside the PRCC block it wants, possible > + values are 0 thru 31. > + type: object > + > + properties: > + '#clock-cells': > + const: 2 > + > + additionalProperties: false > + > + prcc-reset-controller: > + description: A subnode with two reset cells for the reset portions of the > + PRCC (peripheral reset and clock controller). The first cell indicates > + which PRCC block the consumer wants to use, possible values are 1, 2, 3 > + 5 and 6. The second cell indicates which reset line inside the PRCC block > + it wants to control, possible values are 0 thru 31. type: object ? Needs #reset-cells? Though, it doesn't appear to be used, so drop? > + > + rtc32k-clock: > + description: A subnode with zero clock cells for the 32kHz RTC clock. > + type: object > + > + properties: > + '#clock-cells': > + const: 0 > + > + additionalProperties: false > + > + smp-twd-clock: > + description: A subnode for the ARM SMP Timer Watchdog cluster with zero > + clock cells. > + type: object > + > + properties: > + '#clock-cells': > + const: 0 > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + - prcmu-clock > + - prcc-periph-clock > + - prcc-kernel-clock > + - rtc32k-clock > + - smp-twd-clock > + > +additionalProperties: false
