On 2021-07-09 05:40, Stephen Boyd wrote:
Quoting Shaik Sajida Bhanu (2021-06-27 07:42:30)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index a8c274a..c3e8740e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -436,6 +441,60 @@
#mbox-cells = <2>;
};
+ sdhc_1: sdhci@7c4000 {
+ compatible = "qcom,sc7280-sdhci",
"qcom,sdhci-msm-v5";
Is qcom,sc7280-sdhci compatible documented somewhere?
Yes, please find the link below:
https://patchwork.kernel.org/project/linux-arm-msm/patch/1623835207-29462-1-git-send-email-sbhanu@xxxxxxxxxxxxxx/
+ status = "disabled";
+
+ reg = <0 0x007c4000 0 0x1000>,
+ <0 0x007c5000 0 0x1000>;
+ reg-names = "hc", "cqhci";
+
+ iommus = <&apps_smmu 0xc0 0x0>;
+ interrupts = <GIC_SPI 652
IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 656
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "core", "iface", "xo";
+ interconnects = <&aggre1_noc MASTER_SDCC_1 0
&mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0
&cnoc2 SLAVE_SDCC_1 0>;
+ interconnect-names = "sdhc-ddr","cpu-sdhc";
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+
+ bus-width = <8>;
+ supports-cqe;
+
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+
+ sdhc1_opp_table: sdhc1-opp-table {
Please make it
sdhc1_opp_table: opp-table {
Sure
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64
<100000000>;
+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1800000
400000>;
+ opp-avg-kBps = <100000 0>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64
<384000000>;
+ required-opps =
<&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000
1600000>;
+ opp-avg-kBps = <390000 0>;
+ };
+ };
+
+ };
+
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x009c0000 0 0x2000>;
@@ -1035,6 +1094,51 @@
};
};
+ sdhc_2: sdhci@8804000 {
+ compatible = "qcom,sc7280-sdhci",
"qcom,sdhci-msm-v5";
+ status = "disabled";
+
+ reg = <0 0x08804000 0 0x1000>;
+
+ iommus = <&apps_smmu 0x100 0x0>;
+ interrupts = <GIC_SPI 207
IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223
IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_APPS_CLK>,
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "core", "iface", "xo";
+ interconnects = <&aggre1_noc MASTER_SDCC_2 0
&mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0
&cnoc2 SLAVE_SDCC_2 0>;
+ interconnect-names = "sdhc-ddr","cpu-sdhc";
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ bus-width = <4>;
+
+ qcom,dll-config = <0x0007642c>;
+
+ sdhc2_opp_table: sdhc2-opp-table {
Please make it
sdhc2_opp_table: opp-table {
Sure
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64
<100000000>;
+ required-opps =
<&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1800000
400000>;
+ opp-avg-kBps = <100000 0>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64
<202000000>;
+ required-opps =
<&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000
1600000>;
+ opp-avg-kBps = <200000 0>;
+ };
+ };
+
+ };
+
dc_noc: interconnect@90e0000 {
reg = <0 0x090e0000 0 0x5080>;
compatible = "qcom,sc7280-dc-noc";
