Document the bindings for Hikey 960 (hi3660) PCIe PHY interface, supported via the pcie-kirin driver. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@xxxxxxxxxx> --- .../phy/hisilicon,phy-hi3660-pcie.yaml | 70 +++++++++++++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 11 +-- 2 files changed, 76 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml new file mode 100644 index 000000000000..e91a38450461 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3660-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Kirin960 PCIe PHY + +maintainers: + - Mauro Carvalho Chehab <mchehab+huawei@xxxxxxxxxx> + +description: |+ + Bindings for PCIe PHY on HiSilicon Kirin 960. + +properties: + compatible: + const: hisilicon,hi960-pcie-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + description: PHY Control registers + + reg-names: + const: phy + + clocks: + items: + - description: PCIe PHY clock + - description: PCIe APB PHY clock + + clock-names: + items: + - const: pcie_phy_ref + - const: pcie_apb_phy + + reset-gpios: + description: PCI PERST reset GPIO(s) + +required: + - "#phy-cells" + - compatible + - reg + - reg-names + - clocks + - clock-names + - reset-gpios + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie_phy: pcie-phy@f3f2000 { + compatible = "hisilicon,hi960-pcie-phy"; + reg = <0x0 0xf3f20000 0x0 0x40000>; + reg-names = "phy"; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>; + clock-names = "pcie_phy_ref", "pcie_apb_phy"; + reset-gpios = <&gpio11 1 0 >; + #phy-cells = <0>; + }; + }; +... diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3a589fa4ca81..96c978db12dc 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1006,8 +1006,10 @@ pcie_phy: pcie-phy@f3f2000 { reg = <0x0 0xf3f20000 0x0 0x40000>; reg-names = "phy"; clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>; - clock-names = "pcie_phy_ref", "pcie_apb_phy"; + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_apb_phy", + "pcie_aclk"; reset-gpios = <&gpio11 1 0 >; #phy-cells = <0>; }; @@ -1040,9 +1042,8 @@ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_aux", "pcie_apb_sys", "pcie_aclk"; + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>; + clock-names = "pcie_aux", "pcie_apb_sys"; }; /* UFS */ -- 2.31.1
