On 30/06/2021 11:07, Kansho Nishida wrote:
> Add afe (audio front end) device node to the MT8183 dtsi.
>
> Signed-off-by: Kansho Nishida <kansho@xxxxxxxxxxxx>
> ---
>
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 94 +++++++++++++++++++++++-
> 1 file changed, 93 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index f90df6439c08..b06acb8d6527 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -1115,10 +1115,102 @@ usb_host: usb@11200000 {
> };
> };
>
> - audiosys: syscon@11220000 {
> + audiosys: clock-controller@11220000 {
Why do you change it from sysecon to clock-controller?
Regards,
Matthias
> compatible = "mediatek,mt8183-audiosys", "syscon";
> reg = <0 0x11220000 0 0x1000>;
> #clock-cells = <1>;
> + afe: mt8183-afe-pcm {
> + compatible = "mediatek,mt8183-audio";
> + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
> + resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
> + reset-names = "audiosys";
> + power-domains =
> + <&spm MT8183_POWER_DOMAIN_AUDIO>;
> + clocks = <&audiosys CLK_AUDIO_AFE>,
> + <&audiosys CLK_AUDIO_DAC>,
> + <&audiosys CLK_AUDIO_DAC_PREDIS>,
> + <&audiosys CLK_AUDIO_ADC>,
> + <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>,
> + <&audiosys CLK_AUDIO_22M>,
> + <&audiosys CLK_AUDIO_24M>,
> + <&audiosys CLK_AUDIO_APLL_TUNER>,
> + <&audiosys CLK_AUDIO_APLL2_TUNER>,
> + <&audiosys CLK_AUDIO_I2S1>,
> + <&audiosys CLK_AUDIO_I2S2>,
> + <&audiosys CLK_AUDIO_I2S3>,
> + <&audiosys CLK_AUDIO_I2S4>,
> + <&audiosys CLK_AUDIO_TDM>,
> + <&audiosys CLK_AUDIO_TML>,
> + <&infracfg CLK_INFRA_AUDIO>,
> + <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
> + <&topckgen CLK_TOP_MUX_AUDIO>,
> + <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
> + <&topckgen CLK_TOP_SYSPLL_D2_D4>,
> + <&topckgen CLK_TOP_MUX_AUD_1>,
> + <&topckgen CLK_TOP_APLL1_CK>,
> + <&topckgen CLK_TOP_MUX_AUD_2>,
> + <&topckgen CLK_TOP_APLL2_CK>,
> + <&topckgen CLK_TOP_MUX_AUD_ENG1>,
> + <&topckgen CLK_TOP_APLL1_D8>,
> + <&topckgen CLK_TOP_MUX_AUD_ENG2>,
> + <&topckgen CLK_TOP_APLL2_D8>,
> + <&topckgen CLK_TOP_MUX_APLL_I2S0>,
> + <&topckgen CLK_TOP_MUX_APLL_I2S1>,
> + <&topckgen CLK_TOP_MUX_APLL_I2S2>,
> + <&topckgen CLK_TOP_MUX_APLL_I2S3>,
> + <&topckgen CLK_TOP_MUX_APLL_I2S4>,
> + <&topckgen CLK_TOP_MUX_APLL_I2S5>,
> + <&topckgen CLK_TOP_APLL12_DIV0>,
> + <&topckgen CLK_TOP_APLL12_DIV1>,
> + <&topckgen CLK_TOP_APLL12_DIV2>,
> + <&topckgen CLK_TOP_APLL12_DIV3>,
> + <&topckgen CLK_TOP_APLL12_DIV4>,
> + <&topckgen CLK_TOP_APLL12_DIVB>,
> + /*<&topckgen CLK_TOP_APLL12_DIV5>,*/
> + <&clk26m>;
> + clock-names = "aud_afe_clk",
> + "aud_dac_clk",
> + "aud_dac_predis_clk",
> + "aud_adc_clk",
> + "aud_adc_adda6_clk",
> + "aud_apll22m_clk",
> + "aud_apll24m_clk",
> + "aud_apll1_tuner_clk",
> + "aud_apll2_tuner_clk",
> + "aud_i2s1_bclk_sw",
> + "aud_i2s2_bclk_sw",
> + "aud_i2s3_bclk_sw",
> + "aud_i2s4_bclk_sw",
> + "aud_tdm_clk",
> + "aud_tml_clk",
> + "aud_infra_clk",
> + "mtkaif_26m_clk",
> + "top_mux_audio",
> + "top_mux_aud_intbus",
> + "top_syspll_d2_d4",
> + "top_mux_aud_1",
> + "top_apll1_ck",
> + "top_mux_aud_2",
> + "top_apll2_ck",
> + "top_mux_aud_eng1",
> + "top_apll1_d8",
> + "top_mux_aud_eng2",
> + "top_apll2_d8",
> + "top_i2s0_m_sel",
> + "top_i2s1_m_sel",
> + "top_i2s2_m_sel",
> + "top_i2s3_m_sel",
> + "top_i2s4_m_sel",
> + "top_i2s5_m_sel",
> + "top_apll12_div0",
> + "top_apll12_div1",
> + "top_apll12_div2",
> + "top_apll12_div3",
> + "top_apll12_div4",
> + "top_apll12_divb",
> + /*"top_apll12_div5",*/
> + "top_clk26m_clk";
> + };
> };
>
> mmc0: mmc@11230000 {
>
