Hi "周琰杰, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on clk/clk-next] [also build test WARNING on robh/for-next v5.13 next-20210628] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Zhou-Yanjie/Add-new-clocks-and-fix-bugs-for-Ingenic-SoCs/20210629-022157 base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next config: x86_64-randconfig-m001-20210628 (attached as .config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@xxxxxxxxx> smatch warnings: drivers/clk/ingenic/cgu.c:309 ingenic_pll_set_rate() warn: always true condition '(pll_info->stable_bit >= 0) => (0-255 >= 0)' vim +309 drivers/clk/ingenic/cgu.c 272 273 static int 274 ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, 275 unsigned long parent_rate) 276 { 277 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 278 struct ingenic_cgu *cgu = ingenic_clk->cgu; 279 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); 280 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; 281 unsigned long rate, flags; 282 unsigned int m, n, od; 283 int ret = 0; 284 u32 ctl; 285 286 rate = ingenic_pll_calc(clk_info, req_rate, parent_rate, 287 &m, &n, &od); 288 if (rate != req_rate) 289 pr_info("ingenic-cgu: request '%s' rate %luHz, actual %luHz\n", 290 clk_info->name, req_rate, rate); 291 292 spin_lock_irqsave(&cgu->lock, flags); 293 ctl = readl(cgu->base + pll_info->reg); 294 295 ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift); 296 ctl |= (m - pll_info->m_offset) << pll_info->m_shift; 297 298 ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift); 299 ctl |= (n - pll_info->n_offset) << pll_info->n_shift; 300 301 if (pll_info->od_encoding) { 302 ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); 303 ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; 304 } 305 306 writel(ctl, cgu->base + pll_info->reg); 307 308 /* If the PLL is enabled, verify that it's stable */ > 309 if ((pll_info->stable_bit >= 0) && (ctl & BIT(pll_info->enable_bit))) 310 ret = ingenic_pll_check_stable(cgu, pll_info); 311 312 spin_unlock_irqrestore(&cgu->lock, flags); 313 314 return ret; 315 } 316 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
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