Re: [PATCH v3 3/9] clk: si5341: Avoid divide errors due to bogus register contents

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Quoting Robert Hancock (2021-03-25 12:26:37)
> If the Si5341 is being initially programmed and has no stored NVM
> configuration, some of the register contents may contain unexpected
> values, such as zeros, which could cause divide by zero errors during
> driver initialization. Trap errors caused by zero registers or zero clock
> rates which could result in divide errors later in the code.
> 
> Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver")
> Signed-off-by: Robert Hancock <robert.hancock@xxxxxxxxxx>
> ---

Applied to clk-next




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