Quoting Liam Beguin (2021-04-22 17:40:56) > From: Liam Beguin <lvb@xxxxxxxxxx> > > The digital delay allows outputs to be delayed from 8 to 1023 VCO > cycles. The delay step can be as small as half the period of the clock > distribution path. For example, a 3.2-GHz VCO frequency results in > 156.25-ps steps. The digital delay value takes effect on the clock > output phase after a SYNC event. > > This is required to support JESD204B subclass 1. > > Signed-off-by: Liam Beguin <lvb@xxxxxxxxxx> > --- Applied to clk-next
