On Fri 25 Jun 05:21 CDT 2021, Iskren Chernev wrote: > Add device tree binding Documentation details for Qualcomm SM6115 and > SM4250 pinctrl. > > Signed-off-by: Iskren Chernev <iskren.chernev@xxxxxxxxx> Reviewed-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx> Regards, Bjorn > --- > .../bindings/pinctrl/qcom,sm6115-pinctrl.yaml | 182 ++++++++++++++++++ > 1 file changed, 182 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml > new file mode 100644 > index 000000000000..34d57a5c5f75 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml > @@ -0,0 +1,182 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block > + > +maintainers: > + - Iskren Chernev <iskren.chernev@xxxxxxxxx> > + > +description: > + This binding describes the Top Level Mode Multiplexer block found in the > + SM6115 and SM4250 platforms. > + > +properties: > + compatible: > + enum: > + - qcom,sm4250-tlmm > + - qcom,sm6115-tlmm > + > + reg: > + minItems: 3 > + maxItems: 3 > + > + reg-names: > + items: > + - const: west > + - const: south > + - const: east > + > + interrupts: > + description: Specifies the TLMM summary IRQ > + maxItems: 1 > + > + interrupt-controller: true > + > + '#interrupt-cells': > + description: > + Specifies the PIN numbers and Flags, as defined in defined in > + include/dt-bindings/interrupt-controller/irq.h > + const: 2 > + > + gpio-controller: true > + > + '#gpio-cells': > + description: Specifying the pin number and flags, as defined in > + include/dt-bindings/gpio/gpio.h > + const: 2 > + > + gpio-ranges: > + maxItems: 1 > + > + wakeup-parent: > + maxItems: 1 > + > +#PIN CONFIGURATION NODES > +patternProperties: > + '-state$': > + oneOf: > + - $ref: "#/$defs/qcom-sm6115-tlmm-state" > + - patternProperties: > + ".*": > + $ref: "#/$defs/qcom-sm6115-tlmm-state" > + > +'$defs': > + qcom-sm6115-tlmm-state: > + type: object > + description: > + Pinctrl node's client devices use subnodes for desired pin configuration. > + Client device subnodes use below standard properties. > + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" > + > + properties: > + pins: > + description: > + List of gpio pins affected by the properties specified in this > + subnode. > + items: > + oneOf: > + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-3])$" > + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, > + sdc2_clk, sdc2_cmd, sdc2_data ] > + minItems: 1 > + maxItems: 36 > + > + function: > + description: > + Specify the alternative function to be configured for the specified > + pins. > + > + enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c, > + cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0, > + ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio, > + gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist, > + mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte, > + m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag, > + pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti, > + qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb, > + sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk, > + uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, > + uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger, > + wlan1_adc0, elan1_adc1 ] > + > + drive-strength: > + enum: [2, 4, 6, 8, 10, 12, 14, 16] > + default: 2 > + description: > + Selects the drive strength for the specified pins, in mA. > + > + bias-pull-down: true > + > + bias-pull-up: true > + > + bias-disable: true > + > + output-high: true > + > + output-low: true > + > + required: > + - pins > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - interrupt-controller > + - '#interrupt-cells' > + - gpio-controller > + - '#gpio-cells' > + - gpio-ranges > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + tlmm: pinctrl@500000 { > + compatible = "qcom,sm4250-tlmm"; > + reg = <0x500000 0x400000>, > + <0x900000 0x400000>, > + <0xd00000 0x400000>; > + reg-names = "west", "south", "east"; > + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&tlmm 0 0 114>; > + > + sdc2_on_state: sdc2-on-state { > + clk { > + pins = "sdc2_clk"; > + bias-disable; > + drive-strength = <16>; > + }; > + > + cmd { > + pins = "sdc2_cmd"; > + bias-pull-up; > + drive-strength = <10>; > + }; > + > + data { > + pins = "sdc2_data"; > + bias-pull-up; > + drive-strength = <10>; > + }; > + > + sd-cd { > + pins = "gpio88"; > + function = "gpio"; > + bias-pull-up; > + drive-strength = <2>; > + }; > + }; > + }; > + > -- > 2.32.0 >
