Hi Biju,
On Fri, Jun 18, 2021 at 11:58 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> Update clock definitions as per the RZG2L_clock_list(Rev.02) manual.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/include/dt-bindings/clock/r9a07g044-cpg.h
> +++ b/include/dt-bindings/clock/r9a07g044-cpg.h
> +#define R9A07G044_USB_SCLK 73
It looks like USB_SCLK cannot be gated, but is driven directly from
OSCCLK, so I think it should be left out, and the DTS should just
reference R9A07G044_OSCCLK
> +#define R9A07G044_ETH0_CLK_AXI 74
> +#define R9A07G044_ETH0_CLK_CHI 75
> +#define R9A07G044_ETH0_REFCLK 76
> +#define R9A07G044_ETH1_CLK_AXI 77
> +#define R9A07G044_ETH1_CLK_CHI 78
> +#define R9A07G044_ETH1_REFCLK 79
According to the Hardware User's Manual, ETH0_REFCLK and ETH1_REFCLK
cannot be gated (see the note for CPG_CLKMON_ETH), so I think it
should be left out, and the DTS should just reference R9A07G044_CLK_HP.
The rest of the clocks look good to me. Some are still missing, but they
can be added later.
I do think we need a separate list of definitions for resets. While
simple modules like SCIF and I2C have a one-to-one mapping from
clock bits to reset bits for, this is not the case for all modules.
E.g. SDHI has 4 clocks per instance, but only a single reset signal
per instance, while CANFD has a single clock, but two reset signals.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
