On 07/22/2014 11:47 AM, Felipe Balbi wrote: > On Tue, Jul 22, 2014 at 10:39:54AM -0500, Nishanth Menon wrote: >> The DRA74/72 control module pins have a weak pull up and pull down. >> This is configured by bit offset 17. if BIT(17) is 1, a pull up is >> selected, else a pull down is selected. >> >> However, this pull resisstor is applied based on BIT(16) - >> PULLUDENABLE - if BIT(18) is *0*, then pull as defined in BIT(17) is >> applied, else no weak pulls are applied. We defined this in reverse. >> >> Reference: Table 18-5 (Description of the pad configuration register >> bits) in Technical Reference Manual Revision (DRA74x revision Q: >> SPRUHI2Q Revised June 2014 and DRA72x revision F: SPRUHP2F - Revised >> June 2014) >> >> Fixes: 6e58b8f1daaf1a ("ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm board") >> Signed-off-by: Nishanth Menon <nm@xxxxxx> >> --- > > Tested on an upcoming board. > > Tested-by: Felipe Balbi <balbi@xxxxxx> > Acked-by: Felipe Balbi <balbi@xxxxxx> > > Felipe, Thanks. Tony, If you could consider this for the rc cycle it might be great(as well as for stable). The pull direction error can cause all kinds of Pull-down Vs Pull-Up contention with severe risk for certain IP reliability. -- Regards, Nishanth Menon -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html