On 13:05-20210614, Suman Anna wrote:
> >> +&oc_sram {
> >> + main_r5fss0_core0_sram: r5f-sram@40000 {
> >> + reg = <0x40000 0x40000>;
> >> + };
> >> +
> >> + main_r5fss0_core1_sram: r5f-sram@80000 {
> >> + reg = <0x80000 0x40000>;
> >> + };
> >> +
> >> + main_r5fss1_core0_sram: r5f-sram@c0000 {
> >> + reg = <0xc0000 0x40000>;
> >> + };
> >> +
> >> + main_r5fss1_core1_sram: r5f-sram@100000 {
> >> + reg = <0x100000 0x40000>;
> >> + };
> >> +};
> >
>
> These addresses are currently in sync with the corresponding firmware linker map
> files. Any changes needed here should also be aligned and updated with all the
> firmwares then.
>
> Nishanth,
> How about dropping this patch until we conclude the discussion and picking up
> the rest?
Lets skip this patch for this merge cycle - aka stay compatible with the
previous reference binaries that do not use OCSRAM (aka not pick up
4x latency improvement), till we figure out a future looking and
relatively stable memory map that considers:
a) R5s IPC RAM
+ future usage:
b) M4F IPC RAM
c) ICSSG buffer RAMs
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
