From: Jianjun Wang <jianjun.wang@xxxxxxxxxxxx>
Add PCIe phy device node for mt8195 SoC.
Signed-off-by: Jianjun Wang <jianjun.wang@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 80a272703879..dd5644410fea 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1107,6 +1107,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x11e30000 0xe00>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
status = "disabled";
u2port1: usb-phy@0 {
@@ -1146,6 +1147,19 @@
};
};
+ pciephy: phy@11e80000 {
+ compatible = "mediatek,mt8195-pcie-phy";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #phy-cells = <0>;
+ reg = <0 0x11e80000 0 0x10000>,
+ <0 0x11e90000 0 0x10000>;
+ reg-names = "phy-sif", "phy-ckm";
+
+ power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
+ status = "disabled";
+ };
+
ufsphy: phy@11fa0000 {
compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
reg = <0 0x11fa0000 0 0xc000>;
--
2.18.0
