From: Tianping Fang <tianping.fang@xxxxxxxxxxxx>
Add usb support for mt8195 SoC.
Signed-off-by: Tianping Fang <tianping.fang@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 110 ++++++++++++++++++++---
1 file changed, 100 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 1a281551d011..41d9f167701f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -957,6 +957,28 @@
status = "disabled";
};
+ xhci: xhci@11200000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_SEL>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>,
+ <&topckgen CLK_TOP_SSUSB_REF>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+ };
+
mmc0: mmc@11230000 {
compatible = "mediatek,mt8195-mmc",
"mediatek,mt8192-mmc",
@@ -987,6 +1009,70 @@
status = "disabled";
};
+ xhci1: xhci1@11290000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11290000 0 0x1000>,
+ <0 0x11293e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port1 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_1P_SEL>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_1P_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>,
+ <&topckgen CLK_TOP_SSUSB_P1_REF>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+ };
+
+ xhci2: xhci2@112a0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112a0000 0 0x1000>,
+ <0 0x112a3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_2P_SEL>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_2P_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>,
+ <&topckgen CLK_TOP_SSUSB_P2_REF>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+ };
+
+ xhci3: xhci3@112b0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112b0000 0 0x1000>,
+ <0 0x112b3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port3 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_3P_SEL>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_3P_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>,
+ <&topckgen CLK_TOP_SSUSB_P3_REF>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ usb2-lpm-disable;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+ };
+
pcie0: pcie@112f0000 {
device_type = "pci";
compatible = "mediatek,mt8195-pcie";
@@ -1080,7 +1166,7 @@
u2port2: usb-phy@0 {
reg = <0x0 0x700>;
- clocks = <&clk26m>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
clock-names = "ref";
#phy-cells = <1>;
};
@@ -1095,7 +1181,7 @@
u2port3: usb-phy@0 {
reg = <0x0 0x700>;
- clocks = <&clk26m>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
clock-names = "ref";
#phy-cells = <1>;
};
@@ -1244,15 +1330,17 @@
u2port1: usb-phy@0 {
reg = <0x0 0x700>;
- clocks = <&clk26m>;
- clock-names = "ref";
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
+ <&apmixedsys CLK_APMIXED_USB1PLL>;
+ clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
u3port1: usb-phy@700 {
reg = <0x700 0x700>;
- clocks = <&clk26m>;
- clock-names = "ref";
+ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
+ <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
+ clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
};
@@ -1266,15 +1354,17 @@
u2port0: usb-phy@0 {
reg = <0x0 0x700>;
- clocks = <&clk26m>;
- clock-names = "ref";
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
+ <&apmixedsys CLK_APMIXED_USB1PLL>;
+ clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
u3port0: usb-phy@700 {
reg = <0x700 0x700>;
- clocks = <&clk26m>;
- clock-names = "ref";
+ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
+ <&topckgen CLK_TOP_SSUSB_PHY_REF>;
+ clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
};
--
2.18.0
