From: Zhiqiang Ma <zhiqiang.ma@xxxxxxxxxxxx>
add support of pinctrl for mt8195 soc.
Signed-off-by: Zhiqiang Ma <zhiqiang.ma@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 8cda62f736b3..640f09100bb7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/reset/ti-syscon.h>
/ {
@@ -288,6 +289,27 @@
};
};
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt8195-pinctrl";
+ reg = <0 0x10005000 0 0x1000>,
+ <0 0x11d10000 0 0x1000>,
+ <0 0x11d30000 0 0x1000>,
+ <0 0x11d40000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11eb0000 0 0x1000>,
+ <0 0x11f40000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
+ "iocfg_br", "iocfg_lm", "iocfg_rb",
+ "iocfg_tl", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 144>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
+ #interrupt-cells = <2>;
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8195-wdt", "mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
--
2.18.0
