On Mon, Jun 14, 2021 at 3:08 PM Marc Zyngier <maz@xxxxxxxxxx> wrote: > > On Sun, 13 Jun 2021 13:25:40 +0100, > Anup Patel <anup@xxxxxxxxxxxxxx> wrote: > > > > On Sun, Jun 13, 2021 at 3:11 PM Marc Zyngier <maz@xxxxxxxxxx> wrote: > > > > > > I'm sorry, but this really isn't an irqchip driver. This is a piece of > > > arch-specific code that uses *none* of the irq subsystem abstractions > > > apart from the IRQCHIP_DECLARE() macro. > > > > Yes, I was not sure we can call it IRQCHIP hence the RFC PATCH. > > > > Both ACLINT MSWI and SSWI are special devices providing only IPI > > support so I will re-think how to fit this. > > It depends on how you think of IPIs in your architecture. > > arm64 (and even now 32bit) have been moved to a mode where IPIs are > normal interrupts, as it helps with other things such as our pseudo > NMIs, and reduces code duplication. MIPS has done the same for a long > time (they don't have dedicated HW for that). RISC-V is also moving in a similar direction with the RISC-V advanced interrupt architecture (AIA) specification which aims at defining an interrupt controller having MSI support, virtualization support and scalable for a large number of CPUs. The RISC-V AIA treats IPIs as normal interrupts. The RISC-V ACLINT based IPI support is for RISC-V systems which only need a simple interrupt controller without MSI support and virtualization support. These systems will not implement RISC-V AIA. Regards, Anup > > M. > > -- > Without deviation from the norm, progress is not possible.
