We add DT bindings documentation for the ACLINT MTIMER device found on RISC-V SOCs. Signed-off-by: Anup Patel <anup.patel@xxxxxxx> --- .../bindings/timer/riscv,aclint-mtimer.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml new file mode 100644 index 000000000000..21c718f8ab4c --- /dev/null +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V ACLINT M-level Timer + +maintainers: + - Anup Patel <anup.patel@xxxxxxx> + +description: + RISC-V SOCs include an implementation of the M-level timer (MTIMER) defined + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. The + ACLINT MTIMER device is documented in the RISC-V ACLINT specification found + at https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc. + + The ACLINT MTIMER device directly connect to the M-level timer interrupt + lines of various HARTs (or CPUs) so the RISC-V per-HART (or per-CPU) local + interrupt controller is the parent interrupt controller for the ACLINT + MTIMER device. + + The clock frequency of ACLINT is specified via "timebase-frequency" DT + property of "/cpus" DT node. The "timebase-frequency" DT property is + described in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + items: + - const: riscv,aclint-mtimer + + description: + Should be "<vendor>,<chip>-aclint-mtimer" and "riscv,aclint-mtimer". + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + timer@2004000 { + compatible = "riscv,aclint-mtimer"; + interrupts-extended = <&cpu1intc 7 &cpu2intc 7 &cpu3intc 7 &cpu4intc 7>; + reg = <0x2004000 0x8000>; + }; +... -- 2.25.1
