On Thu, Jun 10, 2021 at 08:04:13PM +0530, Manivannan Sadhasivam wrote:
> On Thu, May 27, 2021 at 04:16:42PM +0300, Cristian Ciocaltea wrote:
> > There are a few issues with the setup of the Actions Semi Owl S500 SoC's
> > clock chain involving AHPPREDIV, H and AHB clocks:
> >
> > * AHBPREDIV clock is defined as a muxer only, although it also acts as
> > a divider.
> > * H clock is using a wrong divider register offset
> > * AHB is defined as a multi-rate factor clock, but it is actually just
> > a fixed pass clock.
> >
> > Let's provide the following fixes:
> >
> > * Change AHBPREDIV clock to an ungated OWL_COMP_DIV definition.
> > * Use the correct register shift value in the OWL_DIVIDER definition
> > for H clock
> > * Drop the unneeded 'ahb_factor_table[]' and change AHB clock to an
> > ungated OWL_COMP_FIXED_FACTOR definition.
[...]
> > /* composite clocks */
> > +static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p,
> > + OWL_MUX_HW(CMU_BUSCLK1, 8, 3),
> > + { 0 },
> > + OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
> > + 0);
> > +
> > +static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk",
> > + { 0 },
> > + 1, 1, CLK_SET_RATE_PARENT);
>
> I think you swapped the flags between "ahbprediv_clk" and "ahb_clk"...
Thanks for noticing this, I fixed it in v3:
https://lore.kernel.org/lkml/cover.1623354574.git.cristian.ciocaltea@xxxxxxxxx/
> > +
> > static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
> > OWL_MUX_HW(CMU_VCECLK, 4, 2),
> > OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
> > --
> > 2.31.1
> >
