On Thu, Jun 10, 2021 at 10:20:30AM +0200, Miquel Raynal wrote: > The SMC bus controller features several register sets. The one pointed > by the reg property is for the SMC configuration (impacts the > sub-controllers configuration), while the others are meant to be used to > send regular cycles on the memory bus (eg. CMD, ADDR, DATA for a NAND > device). Detail this a little bit for the sake of clarity. > > Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> > --- > .../devicetree/bindings/memory-controllers/pl353-smc.txt | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt > index ecd46856f139..ba6a5426f62b 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt > +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt > @@ -5,7 +5,8 @@ of memory interfaces: NAND and memory mapped interfaces (such as SRAM or NOR). > > Required properties: > - compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell". > -- reg : Controller registers map and length. > +- reg : SMC controller and sub-controllers configuration > + registers. I think you could just drop this patch. Otherwise, this doesn't match what's now in the yaml file. Rob
