On 2021-05-08 01:29, Stephen Boyd wrote:
Quoting Prasad Malisetty (2021-05-07 03:17:26)
Document the PCIe DT bindings for SC7280 SoC.The PCIe IP is similar
to the one used on SM8250. Add the compatible for SC7280.
Signed-off-by: Prasad Malisetty <pmaliset@xxxxxxxxxxxxxx>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 17
+++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 0da458a..e5245ed 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -12,6 +12,7 @@
- "qcom,pcie-ipq4019" for ipq4019
- "qcom,pcie-ipq8074" for ipq8074
- "qcom,pcie-qcs404" for qcs404
+ - "qcom,pcie-sc7280" for sc7280
- "qcom,pcie-sdm845" for sdm845
- "qcom,pcie-sm8250" for sm8250
@@ -133,6 +134,22 @@
- "slave_bus" AXI Slave clock
- clock-names:
+ Usage: required for sc7280
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "aux" Auxiliary clock
+ - "cfg" Configuration clock
+ - "bus_master" Master AXI clock
+ - "bus_slave" Slave AXI clock
+ - "slave_q2a" Slave Q2A clock
+ - "tbu" PCIe TBU clock
+ - "ddrss_sf_tbu" PCIe SF TBU clock
+ - "pipe" PIPE clock
+ - "pipe_src" PIPE MUX
Is pipe_src necessary? Is it the parent of the pipe clk? If so, please
remove it and do whatever is necessary on the pipe clk instead of the
parent of the clk.
Here pipe_src is MUX. Newer targets require changing pipe-clk mux to
switch between pipe_clk and XO for GDSC enable.
After PHY init, need to configure MUX.
+ - "pipe_ext" PIPE output clock
Is pipe output different from pipe?
Yes, pipe_ext clock will generate after PHY init.
+ - "ref" REFERENCE clock
+
