Bjorn, On Mon, May 10, 2021 at 7:53 AM Douglas Anderson <dianders@xxxxxxxxxxxx> wrote: > > From: Wenchao Han <hanwenchao@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> > > On coachz it could be observed that SPI_CLK voltage level was only > 1.4V during active transfers because the drive strength was too > weak. The line hadn't finished slewing up by the time we started > driving it down again. Using a drive strength of 8 lets us achieve the > correct voltage level of 1.8V. > > Though the worst problems were observed on coachz hardware, let's do > this across the board for trogdor devices. Scoping other boards shows > that this makes the clk line look nicer on them too and doesn't > introduce any problems. > > Only the clk line is adjusted, not any data lines. Because SPI isn't a > DDR protocol we only sample the data lines on either rising or falling > edges, not both. That means the clk line needs to toggle twice as fast > as data lines so having the higher drive strength is more important > there. > > Signed-off-by: Wenchao Han <hanwenchao@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> > [dianders: Adjust author real name; adjust commit message] > Signed-off-by: Douglas Anderson <dianders@xxxxxxxxxxxx> > --- > > arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 + > 1 file changed, 1 insertion(+) I think this patch is ready to land and it's what we're now using in the Chrome OS tree. See <https://crrev.com/c/2821728>. -Doug
