Le lundi 31 mai 2021 à 10:51 +0800, Ming Qian a écrit : > Add devicetree binding documentation for IMX8Q Video Processing Unit IP > > Signed-off-by: Ming Qian <ming.qian@xxxxxxx> > Signed-off-by: Shijie Qin <shijie.qin@xxxxxxx> > Signed-off-by: Zhou Peng <eagle.zhou@xxxxxxx> > --- > .../bindings/media/nxp,imx8q-vpu.yaml | 201 ++++++++++++++++++ > 1 file changed, 201 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml > new file mode 100644 > index 000000000000..97e428dbfdbe > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml > @@ -0,0 +1,201 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > + > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/nxp,imx8q-vpu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX8Q video encode and decode accelerators > + > +maintainers: > + - ming_qian <ming.qian@xxxxxxx> > + - Shijie Qin <shijie.qin@xxxxxxx> > + > +description: |- > + The Amphion MXC video encode and decode accelerators present on NXP i.MX8Q SoCs. Hi, thanks for this work. Do you think it would be possible to give a version for the Amphion design that is in used ? This is for the posterity and/or if some non-NXP vendor needs to use this driver because it picked the same design. Though form what I understood, Allegro acquired it, and might not be continuing that model, it remains that is nicer if we document as much as we can, to give maximum relevance to you rcontribution. > + > +allOf: > + - $ref: /schemas/simple-bus.yaml# > + > +properties: > + compatible: > + items: > + - enum: > + - nxp,imx8qxp-vpu > + - nxp,imx8qm-vpu > + > + reg: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + memory-region: > + description: > + Phandle to a node describing reserved memory used by VPU. > + (see bindings/reserved-memory/reserved-memory.txt) > + > + vpu_lpcg: > + description: > + This is vpu Low-Power Clock Gate (LPCG) module. > + > + mu_m0: > + description: > + Each vpu core correspond a MU node, which used for communication between > + driver and firmware. Implement via mailbox on driver. > + > + vpu_core: > + type: object > + additionalProperties: false > + description: > + Each core correspond a decoder or encoder, need to configure them > + separately. > + > + properties: > + compatible: > + oneOf: > + - const: nxp,imx8q-vpu-decoder > + - const: nxp,imx8q-vpu-encoder > + > + reg: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + mbox-names: > + - const: tx0 > + - const: tx1 > + - const: rx > + > + mboxes: > + maxItems: 3 > + description: > + List of phandle of 2 MU channels for tx, 1 MU channel for rx. > + > + boot-region: > + description: > + Phandle to a node describing reserved memory used by firmware > + loading. > + > + rpc-region: > + description: > + Phandle to a node describing reserved memory used by RPC shared > + memory between firmware and driver. > + > + print-offset: > + description: > + The memory offset from RPC address, used by reserve firmware log. > + > + id: > + description: Index of vpu core. > + > + required: > + - compatible > + - reg > + - power-domains > + - mbox-names > + - mboxes > + - boot-region > + - rpc-region > + - print-offset > + - id > + > + > +required: > + - compatible > + - reg > + - power-domains > + - memory-region > + - vpu_lpcg > + - mu_m0 > + - vpu_core > + > +examples: > + # Device node example for i.MX8QM platform: > + - | > + #include <dt-bindings/firmware/imx/rsrc.h> > + > + vpu: vpu-bus@2c000000 { > + compatible = "nxp,imx8qm-vpu", "simple-bus"; > + ranges = <0x2c000000 0x2c000000 0x2000000>; > + reg = <0x2c000000 0x1000000>; > + #address-cells = <1>; > + #size-cells = <1>; > + power-domains = <&pd IMX_SC_R_VPU>; > + memory-region = <&vpu_reserved>; > + > + vpu_lpcg: clock-controller@2c000000 { > + compatible = "fsl,imx8qxp-lpcg-vpu"; > + reg = <0x2c000000 0x2000000>; > + #clock-cells = <1>; > + status = "disabled"; > + }; > + > + mu_m0: mailbox@2d000000 { > + compatible = "fsl,imx6sx-mu"; > + reg = <0x2d000000 0x20000>; > + interrupts = <0 472 4>; > + #mbox-cells = <2>; > + power-domains = <&pd IMX_SC_R_VPU_MU_0>; > + }; > + > + mu1_m0: mailbox@2d020000 { > + compatible = "fsl,imx6sx-mu"; > + reg = <0x2d020000 0x20000>; > + interrupts = <0 473 4>; > + #mbox-cells = <2>; > + power-domains = <&pd IMX_SC_R_VPU_MU_1>; > + }; > + > + mu2_m0: mailbox@2d040000 { > + compatible = "fsl,imx6sx-mu"; > + reg = <0x2d040000 0x20000>; > + interrupts = <0 474 4>; > + #mbox-cells = <2>; > + power-domains = <&pd IMX_SC_R_VPU_MU_2>; > + }; > + > + vpu_core0: vpu_decoder@2d080000 { > + compatible = "nxp,imx8q-vpu-decoder"; > + reg = <0x2d080000 0x10000>; > + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; > + mbox-names = "tx0", "tx1", "rx"; > + mboxes = <&mu_m0 0 0 > + &mu_m0 0 1 > + &mu_m0 1 0>; > + boot-region = <&decoder_boot>; > + rpc-region = <&decoder_rpc>; > + print-offset = <0x180000>; > + id = <0>; > + }; > + > + vpu_core1: vpu_encoder@2d090000 { > + compatible = "nxp,imx8q-vpu-encoder"; > + reg = <0x2d090000 0x10000>; > + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; > + mbox-names = "tx0", "tx1", "rx"; > + mboxes = <&mu1_m0 0 0 > + &mu1_m0 0 1 > + &mu1_m0 1 0>; > + boot-region = <&encoder1_boot>; > + rpc-region = <&encoder1_rpc>; > + print-offset = <0x80000>; > + id = <1>; > + }; > + > + vpu_core2: vpu_encoder@2d0a0000 { > + reg = <0x2d0a0000 0x10000>; > + compatible = "nxp,imx8q-vpu-encoder"; > + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; > + mbox-names = "tx0", "tx1", "rx"; > + mboxes = <&mu2_m0 0 0 > + &mu2_m0 0 1 > + &mu2_m0 1 0>; > + boot-region = <&encoder2_boot>; > + rpc-region = <&encoder2_rpc>; > + id = <2>; > + }; > + }; > + > +...
