Clock lines may or may not be shared among different CPUs on a platform. When
clock lines are shared between CPUs, they change DVFS state together.
Possible configurations:
1.) All CPUs share a single clock line.
2.) All CPUs have independent clock lines.
3.) CPUs within a group/cluster share clock line but each group/cluster have a
separate line for itself.
There is no generic way available today to detect which CPUs share clock lines
and so this is an attempt towards that.
Much of the information is present in the commit and so no point duplicating it
here.
These are obviously not finalized yet and this is an attempt to initiate a
discussion around this.
Please share your valuable feedback.
Signed-off-by: Viresh Kumar <viresh.kumar@xxxxxxxxxx>
---
I wasn't sure about the path/name of this file, so please don't blast me on that
:)
.../devicetree/bindings/cpufreq/cpu_clocks.txt | 159 +++++++++++++++++++++
1 file changed, 159 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cpufreq/cpu_clocks.txt
diff --git a/Documentation/devicetree/bindings/cpufreq/cpu_clocks.txt b/Documentation/devicetree/bindings/cpufreq/cpu_clocks.txt
new file mode 100644
index 0000000..30ce9ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpu_clocks.txt
@@ -0,0 +1,159 @@
+* Generic CPUFreq clock bindings
+
+Clock lines may or may not be shared among different CPUs on a platform.
+
+Possible configurations:
+1.) All CPUs share a single clock line
+2.) All CPUs have independent clock lines
+3.) CPUs within a group/cluster share clock line but each group/cluster have a
+ separate line for itself
+
+Optional Properties:
+- clock-master: This declares cpu as clock master. Other CPUs can either define
+ "clock-ganged" or "clock-master" property, but shouldn't be missing both.
+
+- clock-ganged: Should have phandle of a cpu declared as "clock-master".
+
+If any cpu node, doesn't have both "clock-master" and "clock-ganged" properties
+defined, it would be assumed that all CPUs on that platform share a single clock
+line. This will help supporting already upstreamed platforms.
+
+
+Examples:
+1.) All CPUs share a single clock line
+
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ clock-master;
+ operating-points = <
+ /* kHz uV */
+ 792000 1100000
+ 396000 950000
+ 198000 850000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ clock-ganged = <&cpu0>;
+ };
+};
+
+OR (clock-master/ganged aren't defined)
+
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ operating-points = <
+ /* kHz uV */
+ 792000 1100000
+ 396000 950000
+ 198000 850000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+};
+
+2.) All CPUs have independent clock lines
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ clock-master;
+ operating-points = <
+ /* kHz uV */
+ 792000 1100000
+ 396000 950000
+ 198000 850000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ clock-master;
+ operating-points = <
+ /* kHz uV */
+ 792000 1100000
+ 396000 950000
+ 198000 850000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ };
+};
+
+3.) CPUs within a group/cluster share single clock line but each group/cluster
+have a separate line for itself
+
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ clock-master;
+ operating-points = <
+ /* kHz uV */
+ 792000 1100000
+ 396000 950000
+ 198000 850000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ clock-ganged = <&cpu0>;
+ };
+
+ cpu2: cpu@100 {
+ compatible = "arm,cortex-a7";
+ reg = <100>;
+ next-level-cache = <&L2>;
+ clock-master;
+ operating-points = <
+ /* kHz uV */
+ 792000 950000
+ 396000 750000
+ 198000 450000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ };
+
+ cpu3: cpu@101 {
+ compatible = "arm,cortex-a7";
+ reg = <101>;
+ next-level-cache = <&L2>;
+ clock-ganged = <&cpu2>;
+ };
+};
--
2.0.0.rc2
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