On Mon, 2021-05-10 at 10:40:51 UTC, Miquel Raynal wrote: > Make use of the cs-gpios DT property as well as the core helper to parse > it so that the Arasan controller driver can now assert many more chips > than natively. > > The Arasan controller has an internal limitation: RB0 is tied to CS0 and > RB1 is tied to CS1. Hence, it is possible to use external GPIOs as long > as one or the other native CS is not used (or configured to be driven as > a GPIO) and that all additional CS are physically wired on its > corresponding RB line. Eg. CS0 is used as a native CS, CS1 is not used > as native CS and may be used as a GPIO CS, CS2 is an additional GPIO > CS. Then the target asserted by CS0 should also be wired to RB0, while > the targets asserted by CS1 and CS2 should be wired to RB1. > > Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> > Reported-by: kernel test robot <lkp@xxxxxxxxx> Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next. Miquel
