The pm8941 and pm8841 spmi devicetree nodes are childrens of
spmi pmic arbiter. The msm8974 SoC uses two PMIC chips
pm8941 and pm8841. Every PMIC chip has two spmi bus slave id's.
Signed-off-by: Stanimir Varbanov <svarbanov@xxxxxxxxxx>
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 37 +++++++++++++++++++++++++++++++++++
1 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 69dca2a..cb05603 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -3,6 +3,7 @@
#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
+#include <dt-bindings/spmi/spmi.h>
/ {
model = "Qualcomm MSM8974";
@@ -236,5 +237,41 @@
#interrupt-cells = <2>;
interrupts = <0 208 0>;
};
+
+ spmi@fc4cf000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg-names = "core", "intr", "cnfg";
+ reg = <0xfc4cf000 0x1000>,
+ <0xfc4cb000 0x1000>,
+ <0xfc4ca000 0x1000>;
+ interrupt-names = "periph_irq";
+ interrupts = <0 190 0>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ usid0: pm8941@0 {
+ compatible = "qcom,pm8941";
+ reg = <0x0 SPMI_USID>;
+ };
+
+ usid1: pm8941@1 {
+ compatible = "qcom,pm8941";
+ reg = <0x1 SPMI_USID>;
+ };
+
+ usid4: pm8841@4 {
+ compatible = "qcom,pm8841";
+ reg = <0x4 SPMI_USID>;
+ };
+
+ usid5: pm8841@5 {
+ compatible = "qcom,pm8841";
+ reg = <0x5 SPMI_USID>;
+ };
+ };
};
};
--
1.7.0.4
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