Am 2021-05-19 20:26, schrieb Miquel Raynal:
[..]
+examples:
+ - |
+ smcc: memory-controller@e000e000 {
+ compatible = "arm,pl353-smc-r2p1", "arm,primecell";
+ reg = <0xe000e000 0x0001000>,
+ <0xe1000000 0x5000000>;
+ clock-names = "memclk", "apb_pclk";
+ clocks = <&clkc 11>, <&clkc 44>;
+ ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
+ 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
+ 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region
*/
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ nand0: nand-controller@0,0 {
what about nfc (or nfc0) here? If I use this reference on my board it
looks kinda odd:
&nand {
status = "okay";
nand@0 {
reg = <0>;
nand-use-soft-ecc-engine;
nand-ecc-algo = "bch";
};
};
-michael