On 10-05-21, 23:19, Bjorn Andersson wrote:
> +static int qcom_edp_phy_power_on(struct phy *phy)
> +{
> + struct qcom_edp *edp = phy_get_drvdata(phy);
> + int timeout;
> + int ret;
> + u32 val;
> +
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> + edp->edp + DP_PHY_PD_CTL);
> + writel(0xfc, edp->edp + DP_PHY_MODE);
> +
> + timeout = readl_poll_timeout(edp->pll + QSERDES_COM_CMN_STATUS,
> + val, val & BIT(7), 5, 200);
> + if (timeout)
> + return timeout;
> +
> + writel(0x01, edp->tx0 + TXn_LDO_CONFIG);
> + writel(0x01, edp->tx1 + TXn_LDO_CONFIG);
> + writel(0x00, edp->tx0 + TXn_LANE_MODE_1);
> + writel(0x00, edp->tx1 + TXn_LANE_MODE_1);
> +
> + ret = qcom_edp_configure_ssc(edp);
> + if (ret)
> + return ret;
> +
> + ret = qcom_edp_configure_pll(edp);
> + if (ret)
> + return ret;
> +
> + /* TX Lane configuration */
> + writel(0x05, edp->edp + DP_PHY_TX0_TX1_LANE_CTL);
> + writel(0x05, edp->edp + DP_PHY_TX2_TX3_LANE_CTL);
> +
> + /* TX-0 register configuration */
> + writel(0x03, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN);
> + writel(0x0f, edp->tx0 + TXn_CLKBUF_ENABLE);
> + writel(0x03, edp->tx0 + TXn_RESET_TSYNC_EN);
> + writel(0x01, edp->tx0 + TXn_TRAN_DRVR_EMP_EN);
> + writel(0x04, edp->tx0 + TXn_TX_BAND);
> +
> + /* TX-1 register configuration */
> + writel(0x03, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);
> + writel(0x0f, edp->tx1 + TXn_CLKBUF_ENABLE);
> + writel(0x03, edp->tx1 + TXn_RESET_TSYNC_EN);
> + writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN);
> + writel(0x04, edp->tx1 + TXn_TX_BAND);
> +
> + ret = qcom_edp_set_vco_div(edp);
> + if (ret)
> + return ret;
> +
> + writel(0x01, edp->edp + DP_PHY_CFG);
> + writel(0x05, edp->edp + DP_PHY_CFG);
> + writel(0x01, edp->edp + DP_PHY_CFG);
> + writel(0x09, edp->edp + DP_PHY_CFG);
> +
> + writel(0x20, edp->pll + QSERDES_COM_RESETSM_CNTRL);
> +
> + timeout = readl_poll_timeout(edp->pll + QSERDES_COM_C_READY_STATUS,
> + val, val & BIT(0), 500, 10000);
> + if (timeout)
> + return timeout;
> +
> + writel(0x19, edp->edp + DP_PHY_CFG);
> + writel(0x1f, edp->tx0 + TXn_HIGHZ_DRVR_EN);
> + writel(0x04, edp->tx0 + TXn_HIGHZ_DRVR_EN);
> + writel(0x00, edp->tx0 + TXn_TX_POL_INV);
> + writel(0x1f, edp->tx1 + TXn_HIGHZ_DRVR_EN);
> + writel(0x04, edp->tx1 + TXn_HIGHZ_DRVR_EN);
> + writel(0x00, edp->tx1 + TXn_TX_POL_INV);
> + writel(0x10, edp->tx0 + TXn_TX_DRV_LVL_OFFSET);
> + writel(0x10, edp->tx1 + TXn_TX_DRV_LVL_OFFSET);
> + writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX0);
> + writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX1);
> + writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0);
> + writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1);
> +
> + writel(0x10, edp->tx0 + TXn_TX_EMP_POST1_LVL);
> + writel(0x10, edp->tx1 + TXn_TX_EMP_POST1_LVL);
> + writel(0x1f, edp->tx0 + TXn_TX_DRV_LVL);
> + writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL);
> +
> + writel(0x4, edp->tx0 + TXn_HIGHZ_DRVR_EN);
> + writel(0x3, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN);
> + writel(0x4, edp->tx1 + TXn_HIGHZ_DRVR_EN);
> + writel(0x0, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);
> + writel(0x3, edp->edp + DP_PHY_CFG_1);
> +
> + writel(0x18, edp->edp + DP_PHY_CFG);
Can't help but think that this should be made modular. We would come up
with next set which would have different set of sequence/values so
having a qmp style table here would be better..
--
~Vinod
