Hi Ikjoon, Thank you for your patch. On 14/4/21 9:31, Ikjoon Jang wrote: > mfgcfg clock is under MFG_ASYNC power domain > > Signed-off-by: Weiyi Lu <weiyi.lu@xxxxxxxxxxxx> > Signed-off-by: Ikjoon Jang <ikjn@xxxxxxxxxxxx> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@xxxxxxxxxxxxx> > --- > > Changes in v2: > Fix a wrong power domain reference (scpsys to spm). > > Link(v1): https://patchwork.kernel.org/project/linux-mediatek/patch/20210224091742.1060508-1-ikjn@xxxxxxxxxxxx/#23997681 > > --- > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 0ff7b67a6806..64813634c3df 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -1116,6 +1116,7 @@ mfgcfg: syscon@13000000 { > compatible = "mediatek,mt8183-mfgcfg", "syscon"; > reg = <0 0x13000000 0 0x1000>; > #clock-cells = <1>; > + power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>; > }; > > mmsys: syscon@14000000 { >
