Hi Fabien, As you might remember this patch didn't hit mainline in the last merge window. Actually there are some concerns about the driver architecture [1]. Apart from that small comment below. [1] https://lore.kernel.org/linux-mediatek/CAK8P3a2Qg-uz0kMXFMrvRjUv3NRvZXjTwS1P5MDvFk3feYaBzg@xxxxxxxxxxxxxx/ On 06/04/2021 13:36, Fabien Parent wrote: > Add all the DRM nodes required to get DSI to work on MT8167 SoC. > > Signed-off-by: Fabien Parent <fparent@xxxxxxxxxxxx> > --- > Note: This series is based on https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.12-next/dts64-2 > > V3: > * Removed unicode character in commit summary > V2: > * No changes > > arch/arm64/boot/dts/mediatek/mt8167.dtsi | 149 +++++++++++++++++++++++ > 1 file changed, 149 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi > index 9029051624a6..17942095944e 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi > @@ -16,6 +16,19 @@ > / { > compatible = "mediatek,mt8167"; > > + aliases { > + aal0 = &aal; > + ccorr0 = &ccorr; > + color0 = &color; > + dither0 = &dither; > + dsi0 = &dsi; > + ovl0 = &ovl0; > + pwm0 = &disp_pwm; > + rdma0 = &rdma0; > + rdma1 = &rdma1; > + wdma0 = &wdma; > + }; > + > soc { > topckgen: topckgen@10000000 { > compatible = "mediatek,mt8167-topckgen", "syscon"; > @@ -114,6 +127,13 @@ vdecsys: syscon@16000000 { > #clock-cells = <1>; > }; > > + mutex: mutex@14015000 { > + compatible = "mediatek,mt8167-disp-mutex"; > + reg = <0 0x14015000 0 0x1000>; > + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; > + }; > + > pio: pinctrl@1000b000 { > compatible = "mediatek,mt8167-pinctrl"; > reg = <0 0x1000b000 0 0x1000>; > @@ -126,6 +146,135 @@ pio: pinctrl@1000b000 { > interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; > }; > > + rdma1: rdma1@1400a000 { > + compatible = "mediatek,mt8167-disp-rdma", > + "mediatek,mt2701-disp-rdma"; > + reg = <0 0x1400a000 0 0x1000>; > + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + iommus = <&iommu M4U_PORT_DISP_RDMA1>; > + mediatek,larb = <&larb0>; > + }; > + > + disp_pwm: disp_pwm@1100f000 { > + compatible = "mediatek,mt8167-disp-pwm", > + "mediatek,mt8173-disp-pwn"; Should be "mediatek,mt8173-disp-pwm" right? I'll un-stage this patch but keep the rest for v5.14. Please re-submit once the driver binding is clarified. Regards, Matthias
