On Sat, 08 May 2021 09:09:26 +0200, Sergio Paracuellos wrote:
> MT7621 SoC clock driver has already mainlined in
> 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")'
> Hence update schema with the add of the entries related to
> clock. Since until now things were not properly being done
> we mark also 'clock' as required in the binding since this
> will be now the only way to properly retrieve frequency to be
> able to make a correct configuration of the PCIe phy registers.
>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
> ---
> .../devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
Acked-by: Rob Herring <robh@xxxxxxxxxx>
