On Wednesday 16 July 2014 01:43 AM, Paul Walmsley wrote: > On Mon, 14 Jul 2014, Kishon Vijay Abraham I wrote: > >> On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote: >>> On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote: >>>> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC. >>>> >>>> Cc: Tony Lindgren <tony@xxxxxxxxxxx> >>>> Cc: Russell King <linux@xxxxxxxxxxxxxxxx> >>>> Cc: Paul Walmsley <paul@xxxxxxxxx> >>>> Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx> >>>> Tested-by: Kishon Vijay Abraham I <kishon@xxxxxx> >>>> --- >>>> Changes from v1: >>>> * changed the clock domain to "pcie_clkdm" >>>> * Added PCIe as a slave port for l3_main. >>> >>> Looks good to me, >>> Reviewed-by: Rajendra Nayak <rnayak@xxxxxx> >> >> Paul, >> >> Can you pick this one? > > Yep, queued for 3.17. Thanks :-) -Kishon > > - Paul > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
