On 5/6/21 5:05 PM, Rob Herring wrote: > On Tue, May 04, 2021 at 02:49:24PM -0400, Sean Anderson wrote: >> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is >> a "soft" block, so it has many parameters which would not be >> configurable in most hardware. This binding is usually automatically >> generated by Xilinx's tools, so the names and values of properties >> must be kept as they are. >> >> Signed-off-by: Sean Anderson <sean.anderson@xxxxxxxx> >> --- >> >> Changes in v2: >> - Use 32-bit addresses for example binding >> >> .../bindings/pwm/xlnx,axi-timer.yaml | 91 +++++++++++++++++++ >> 1 file changed, 91 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> >> diff --git a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> new file mode 100644 >> index 000000000000..bd014134c322 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> @@ -0,0 +1,91 @@ >> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding >> + >> +maintainers: >> + - Sean Anderson <sean.anderson@xxxxxxxx> >> + >> +properties: >> + compatible: >> + items: >> + - const: xlnx,axi-timer-2.0 >> + - const: xlnx,xps-timer-1.00.a >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + const: s_axi_aclk >> + >> + reg: >> + maxItems: 1 >> + >> + xlnx,count-width: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + minimum: 8 >> + maximum: 32 >> + description: >> + The width of the counters, in bits. >> + >> + xlnx,gen0-assert: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + The polarity of the generateout0 signal. 0 for active-low, 1 for active-high. >> + >> + xlnx,gen1-assert: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + The polarity of the generateout1 signal. 0 for active-low, 1 for active-high. >> + >> + xlnx,one-timer-only: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + Whether only one timer is present in this block. >> + >> + xlnx,trig0-assert: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + The polarity of the capturetrig0 signal. 0 for active-low, 1 for active-high. >> + >> + xlnx,trig1-assert: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + The polarity of the capturetrig1 signal. 0 for active-low, 1 for active-high. > > Can't all these be boolean? They could, but > This binding is usually automatically generated by Xilinx's tools, so > the names and values of properties must be kept as they are. Because this is a soft device, the binding may be (very conveniently) auto-generated. I am not opposed to adding additional properties which could be used by new code, but we should still accept this auto-generated output. --Sean > >> + >> +required: >> + - compatible >> + - clocks >> + - reg >> + - xlnx,count-width >> + - xlnx,gen0-assert >> + - xlnx,gen1-assert >> + - xlnx,one-timer-only >> + - xlnx,trig0-assert >> + - xlnx,trig1-assert >> + >> +additionalProperties: true >> + >> +examples: >> + - | >> + axi_timer_0: timer@800e0000 { >> + clock-frequency = <99999001>; >> + clock-names = "s_axi_aclk"; >> + clocks = <&zynqmp_clk 71>; >> + compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a"; >> + reg = <0x800e0000 0x10000>; >> + xlnx,count-width = <0x20>; >> + xlnx,gen0-assert = <0x1>; >> + xlnx,gen1-assert = <0x1>; >> + xlnx,one-timer-only = <0x0>; >> + xlnx,trig0-assert = <0x1>; >> + xlnx,trig1-assert = <0x1>; >> + }; >> -- >> 2.25.1 >>
