MT7621 SoC clock driver has already mainlined in
'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")'
Hence update schema with the add of the entries related to
clock.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
---
.../bindings/phy/mediatek,mt7621-pci-phy.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
index 0ccaded3f245..d8614ef8995c 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
@@ -16,6 +16,14 @@ properties:
reg:
maxItems: 1
+ clocks:
+ maxItems: 1
+ description:
+ PHY reference clock. Must contain an entry in clock-names.
+
+ clock-names:
+ const: sys_clk
+
"#phy-cells":
const: 1
description: selects if the phy is dual-ported
@@ -23,6 +31,8 @@ properties:
required:
- compatible
- reg
+ - clocks
+ - clock-names
- "#phy-cells"
additionalProperties: false
@@ -32,5 +42,7 @@ examples:
pcie0_phy: pcie-phy@1e149000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e149000 0x0700>;
+ clocks = <&sysc 0>;
+ clock-names = "sys_clk";
#phy-cells = <1>;
};
--
2.25.1
