On 2/11/21 11:50 AM, AngeloGioacchino Del Regno wrote:
On some IPA versions (v3.1 and older), writing to registers
GSI_INTER_EE_SRC_CH_IRQ_OFFSET and GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET
will generate a fault and the SoC will lockup.
Avoid clearing CH and EV_CH interrupts on GSI probe to fix this bad
behavior: we are anyway not going to get spurious interrupts.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxxx>
Looking at this more closely, I see that you have found
a *bug* that I will fix. The bug is that these registers
are the IRQ status registers, not the IRQ mask registers.
I have posted a fix for this bug, and once fixed, and I would
like to know whether this fix makes the fault you were
observing go away.
https://lore.kernel.org/netdev/20210505223636.232527-1-elder@xxxxxxxxxx
-Alex
---
drivers/net/ipa/gsi.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c
index 6315336b3ca8..b5460cbb085c 100644
--- a/drivers/net/ipa/gsi.c
+++ b/drivers/net/ipa/gsi.c
@@ -207,11 +207,14 @@ static void gsi_irq_setup(struct gsi *gsi)
iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET);
/* Reverse the offset adjustment for inter-EE register offsets */
- adjust = gsi->version < IPA_VERSION_4_5 ? 0 : GSI_EE_REG_ADJUST;
- iowrite32(0, gsi->virt + adjust + GSI_INTER_EE_SRC_CH_IRQ_OFFSET);
- iowrite32(0, gsi->virt + adjust + GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET);
+ if (gsi->version > IPA_VERSION_3_1) {
+ adjust = gsi->version < IPA_VERSION_4_5 ? 0 : GSI_EE_REG_ADJUST;
+ iowrite32(0, gsi->virt + adjust + GSI_INTER_EE_SRC_CH_IRQ_OFFSET);
+ iowrite32(0, gsi->virt + adjust + GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET);
+ }
iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);
+
}
/* Turn off all GSI interrupts when we're all done */
