29.04.2021 08:51, Krishna Reddy пишет: > Hi Dmitry, > >> Thank you for the answer. Could you please give more information about: >> 1) Are you on software or hardware team, or both? > > I am in the software team and has contributed to initial Tegra SMMU driver in the downstream along with earlier team member Hiroshi Doyu. > >> 2) Is SMMU a third party IP or developed in-house? > > Tegra SMMU is developed in-house. > >> 3) Do you have a direct access to HDL sources? Are you 100% sure that >> hardware does what you say? > > It was discussed with Hardware team before and again today as well. > Enabling ASID for display engine while it continues to access the buffer memory is a safe operation. > As per HW team, The only side-effect that can happen is additional latency to transaction as SMMU caches get warmed up. > >> 4) What happens when CPU writes to ASID register? Does SMMU state machine >> latch ASID status (making it visible) only at a single "safe" point? > > MC makes a decision on routing transaction through either SMMU page tables or bypassing based on the ASID register value. It > checks the ASID register only once per transaction in the pipeline. Thank you very much for the clarification.
