On 4/27/21 8:51 PM, Vignesh Raghavendra wrote:
> Traffic through main NAVSS interconnect is coherent wrt ARM caches on
> J7200 SoC. Add missing dma-coherent property to main_navss node.
>
> Also add dma-ranges to be consistent with mcu_navss node.
and with am65, j721e main and mcu navss...
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@xxxxxxxxx>
> Fixes: d361ed88455fe ("arm64: dts: ti: Add support for J7200 SoC")
> Signed-off-by: Vignesh Raghavendra <vigneshr@xxxxxx>
> ---
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index f86c493a44f1c..a6826f1888ef0 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -85,6 +85,8 @@ main_navss: bus@30000000 {
> #size-cells = <2>;
> ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
> ti,sci-dev-id = <199>;
> + dma-coherent;
> + dma-ranges;
>
> main_navss_intr: interrupt-controller1 {
> compatible = "ti,sci-intr";
>
--
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